Abstract
Over the past three decades, several memory technologies have made their place in the market with varying degrees of commercial success, such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), static random-access memory (SRAM), dynamic RAM (DRAM), and NAND/NOR flash memories, with varying degrees of commercial success. In general, computer systems employ a memory hierarchy using different types of memories used at different levels. At the highest level, on-chip high speed cache static-RAMs (SRAMs) are used; whereas, at the next higher level, high density, low power off-chip DRAMs are used as a main memory.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
H. Yu, Y. Wang, Design Exploration of Emerging Nano-scale Non-volatile Memory, Springer, 2015, ch. 1.
D. Tang and Y. Lee, Magnetic memory fundamentals and technology, 1st ed., Cambridge University Press, 2010, ch. 3–6.
Y. Huai, “Spin-transfer torque MRAM (STT-MRAM): challenges and prospects,” AAPPS Bulletin, vol. 18, no. 6, pp. 33–40, 2008.
R. Bishnoi, M. Ebrahimi, F. Oboril, and M. Tahoori, “Architectural aspects in design and analysis of SOT-based memories,” IEEE Proc. Asia South Pac. Des. Autom. Conf. ASP-DAC, pp. 700–707, 2014.
Y. Kim, S. Member, X. Fong, K. Kwon, M. Chen, and K. Roy, “Multilevel spin-orbit torque MRAMs,” IEEE Trans. Elect. Dev.,vol. 62, no. 2, pp. 561–568, 2015.
K. Wang, J. Alzate, and P. Amiri, “Low-power non-volatile spintronic memory: STT-RAM and beyond,” J. Phys. D, Appl. Phys., vol. 46, no. 7, p. 074003, 2013.
K. Lee, J. Sapan, S. Kang, and E. Fullerton, “Perpendicular magnetization of CoFeB on single-crystal MgO,” J. Appl. Phys., vol. 109, no. 12, pp. 123910-1–123910-3, 2011.
X. Lou, Z. Gao, D. V. Dimitrov, and M. X. Tang, “Demonstration of multilevel cell spin transfer switching in MgO magnetic tunnel junctions,” Appl. Phys. Lett., vol. 93, no. 24, pp. 242502-1–242502-3, 2008.
L. Liu, C.-F. Pai, Y. Li, H. W. Tseng, D. C. Ralph, and R. A. Buhrman,“Spin-torque switching with the giant spin Hall effect of tantalum,” Science, vol. 336, no. 6081, pp. 555–558, 2012.
Y. Zhang, L. Zhang, W. Wen, G. Sun, and Y. Chen, “Multi-level cell STT-RAM: Is it realistic or just a dream?” in Proc. IEEE/ACM Int. Conf. Compu.-Aid. Des. (ICCAD), November, 2012, pp. 526–532.
Y. Chen, W.-F. Wong, H. Li, Y. Zhang, and W. Wen, “On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations,” J. Emer. Techn. Compu. Sys., vol. 9, no.2, May 2013.
Y. Ran, W. Kang, Y. Zhang, J. O. Klein, and W. Zhao, “Read disturbance issue and design techniques for nanoscale STT-MRAM,” J. Sys. Archi., vol. 0, pp. 1–10, 2015.
L.-B. Faber, W. Zhao, J.-O. Klein, T. Devolder, and C. Chappert, “Dynamic compact model of spin-transfer torque based magnetic tunnel junction (MTJ),” in Proc. 4th Int. Conf. Des. Tech. Inte. Sys. Nanosc. Era (DTIS), Apr. 2009, pp. 130–135.
J. Harms, F. Ebrahimi, X. Yao and J. Wang, “SPICE macromodel of spin-torque-transfer-operated magnetic tunnel junctions,” IEEE Trans. Elect. Dev., vol. 57, no. 6, pp. 1425–1430, 2010.
S. Lee, H. Shin, and D. Kim, “Advanced HSPICE macromodel for magnetic tunnel junction,” Jap. J. App. Phy., vol. 44, no. 4B, pp. 2696–2700, 2005.
B. Das, and W. Black Jr., “A generalized HSPICE macro-model for pinned spin-dependent-tunneling devices,” IEEE Trans. on Mag., vol. 35, no. 5, pp. 2889–2891, 1999.
L. Faber, Z. Weisheng, J. Klein, T. Devolder, and C. Chappert, “Dynamic compact model of spin-transfer Torque based Magnetic Tunnel Junction (MTJ),” 4th Int. Conf. on Des. & Tech. of Inte. Sys. in Nano. Era, Cairo, pp. 130–135, 2009.
Y. Zhang, W. Zhao, D. Ravelosona, J. O. Klein, J. V. Kim, and C. Chappert, “A Compact model of perpendicular magnetic anisotropy magnetic tunnel junction,” IEEE Trans. Elect. Dev., vol. 59, no. 3, pp. 819–826, 2012.
J. Kim, A. Chen, B. Behin-aein, S. Kumar, J. Wang, C. H. Kim, and A. M. Anisotropy, “A technology-agnostic MTJ SPICE model with user- defined dimensions for STT-MRAM scalability studies,” IEEE Cust. Inte. Cir. Conf. (CICC), San Jose, 2015, vol. 1, pp. 8–11.
G. D. Panagopoulos, C. Augustine, and K. Roy, “Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits,” IEEE Trans. Elect. Dev., vol. 60, no. 9, pp. 2808–2814, 2013.
M. Kazemi, G. Rowlands, E. Ipek, R. Buhrman, and E. Friedman, “Compact model for spin-orbit magnetic tunnel junctions,” IEEE Trans. Elec. Dev., vol. 63, no. 2, pp. 848–855, 2016.
G. Panagopoulos, C. Augustine, X. Fong, and K. Roy, “Exploring variability and reliability of multi-level STT-MRAM cells,” Dev. Res. Conf. - Conf. Dig. DRC, Texas, USA, June, 2012, pp. 139–140.
T. Ishigaki et al., “A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions,” in Proc. Symp. VLSI Technol. (VLSIT), Jun. 2010, pp. 47–48.
M. Aoki, H. Noshiro, and K. Tsunoda, “Novel highly scalable multi-level cell for STT-MRAM with stacked perpendicular MTJs,” IEEE Symp. on VLSI Tech., June, 2013, pp. 134–135.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2017 The Author(s)
About this chapter
Cite this chapter
Kaushik, B.K., Verma, S., Kulkarni, A.A., Prajapati, S. (2017). Multilevel Cell MRAMs. In: Next Generation Spin Torque Memories. SpringerBriefs in Applied Sciences and Technology. Springer, Singapore. https://doi.org/10.1007/978-981-10-2720-8_4
Download citation
DOI: https://doi.org/10.1007/978-981-10-2720-8_4
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-2719-2
Online ISBN: 978-981-10-2720-8
eBook Packages: EngineeringEngineering (R0)