Abstract
As there are still a lot of challenges on 3D stacking technology, 2.5D stacking technology seems to have better application prospects. With the silicon interposer, the 2.5D stacking can improve the bandwidth and capacity of memory. Moreover, the interposer can be explored to make use of unused routing resources and generates an additional network for communication. In this paper, we conclude that using concentrated Mesh as the topology of the interposer network faces the bottleneck of edge portion, while using Double-Butterfly can overcome this bottleneck. We analyze the reasons that pose the bottleneck, compare impacts of different topologies on bottlenecks and propose design goals for the interposer network.
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Acknowledgements
This work is supported by the National Natural Science Foundation of China (No.6133007, No. 61303065), Doctoral Fund of Ministry of Education (20134307120028).
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Li, C., Wang, Z., Wang, L., Ma, S., Guo, Y. (2016). Overcoming and Analyzing the Bottleneck of Interposer Network in 2.5D NoC Architecture. In: Wu, J., Li, L. (eds) Advanced Computer Architecture. ACA 2016. Communications in Computer and Information Science, vol 626. Springer, Singapore. https://doi.org/10.1007/978-981-10-2209-8_4
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DOI: https://doi.org/10.1007/978-981-10-2209-8_4
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