Abstract
Recently, System-On-a-Chip (SOC) technology can easily design and implement a full system on a single chip (chipset). In order to consume time and cost for designing SOC, Intellectual Property blocks (IPs) or virtual components are used. This IP designs require significant amount of time and effort to be developed and verified.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Group, I.P.P.D.W. 2001. Intellectual property protection: Schemes, alternatives and discussion. VSI Alliance, White Paper, Version, 2001. 1.
Abdel-Hamid, A.T., S. Tahar., and E.M. Aboulhamid. 2003. IP watermarking techniques: Survey and comparison. In Proceedings of the 3rd IEEE international workshop on system-on-chip for real-time applications 2003. IEEE.
Liang, W., et al. 2011. A chaotic IP watermarking in physical layout level based on FPGA. Radioengineering 20(1): 118–125.
Fan, Y.-C., and H.-W. Tsao. 2003. Watermarking for intellectual property protection. Electronics Letters 39(18): 1316–1318.
Chapman, R., and T.S. Durrani. 2000. IP protection of DSP algorithms for system on chip implementation. IEEE Transactions on Signal Processing 48(3): 854–861.
Hong, I., and M. Potkonjak. 1998. Techniques for intellectual property protection of DSP designs. In Proceedings of the 1998 IEEE international conference on acoustics, speech and signal processing, 1998. IEEE.
Oliveira, A.L. 2001. Techniques for the creation of digital watermarks in sequential circuit designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(9): 1101–1117.
Kahng, A.B., et al. 2001. Constraint-based watermarking techniques for design IP protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20(10): 1236–1252.
Megerian, S., M. Drinic., and M. Potkonjak. 2002. Watermarking integer linear programming solutions. In Proceedings of the 39th annual design automation conference. ACM.
Wolfe, G., J.L. Wong, and M. Potkonjak. 2002. Watermarking graph partitioning solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21(10): 1196–1204.
Qu, G., and M. Potkonjak. 2000. Fingerprinting intellectual property using constraint-addition. In Proceedings of the 37th annual design automation conference. ACM.
Charben, E. 1998. Hierarchical watermarking in IC design. In Proceedings of the IEEE custom integrated circuits conference. Citeseer.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2017 Springer Science+Business Media Singapore
About this chapter
Cite this chapter
Nematollahi, M.A., Vorakulpipat, C., Rosales, H.G. (2017). Hardware IP Watermarking. In: Digital Watermarking . Springer Topics in Signal Processing, vol 11. Springer, Singapore. https://doi.org/10.1007/978-981-10-2095-7_12
Download citation
DOI: https://doi.org/10.1007/978-981-10-2095-7_12
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-2094-0
Online ISBN: 978-981-10-2095-7
eBook Packages: EngineeringEngineering (R0)