Abstract
Motivation behind this paper is to bring new method for multi-feature compact designs with low power requirement which is beyond the capacity of binary logic as well as use of only CMOS technology. Simplicity, compactness, and low power requirement can be achieved by hybridization of single electron transistor and CMOS with quaternary logic. The proposed implementation overcomes several limitations found in the previous quaternary implementation such as MIN, MAX, XOR gate and Full Adder which is simulated in 120 nm technology requires less number of transistors as well as with very low power dissipation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Lukasiewicz, “On three valued-logic,” in L. Borkowski, SelectWorks, Amsterdam, North-Holland, 1920, pp. 169–171.
E. L. Post, “Introduction to a general theory of elementary propositions,” Amer. J. Math., vol. 43, no. 3, pp. 163–185, Jul. 1921.
Kenneth C. Smith “ Multiple-Valued Logic: A Tutorial and Appreciation” IEEE Trans. April 1998 PP. 17–27.
Daniel Etiemble and Michel Israel “Comparison of Binary and Multivalued According to VLSI Criteria” IEEE Trans. Computers April 1998 PP. 28–42.
Simulating Hybrid Circuits of Single-Electron Transistors and Field-Effect Transistors Günther LIENTSCHNIG_, Irek WEYMANN and Peter HADLEY, Applied Sciences and DIMES, Delft University of Technology, Lorentzweg 1, 2628 CJ Delft, Netherlands.
Günther LIENTSCHNIG_, Irek WEYMANN and Peter HADLEY “Simulating Hybrid Circuits of Single-Electron Transistors and Field-Effect Transistor”Jpn. J. Appl. Phys. Vol. 42 (2003) pp. 6467–6472 Part 1, No. 10 October 2003.
Vaishali Raut,Dr.P.K.Dakhole “Design And Implementation Of Single Electron Arithmetic And Logic Unit Using Hybrid Single Electron Transistor And Mosfet At 120 nm Technology” 2015 International Conference on Pervasive Computing (ICPC).
Watanabe, T., Matsumoto, M., And Li T., CMOS fourvalued logic circuits using charge-control technique. 18 th Int. Symposium on Multiple-Valued Logic, 1988, pp. 90–97.
I. Thoidis D. Soudris, I. Karafyllidis, S. Christoforidis, A. Thanailakis, “ Quaternary voltage-mode CMOS circuits for multiple-valued logic” IEEE proceeding 145.1998. pp.
Ms. Vaishali Raut, Dr. P. K. Dakhole “Design And Implementation Of Single Electron Transistor N-BIT Multiplier” [ICCPCT]-978-1-4799-2395-3.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2017 Springer Science+Business Media Singapore
About this paper
Cite this paper
Raut Vaishali, Dakhole, P.K. (2017). Design and Simulation of Hybrid SETMOS Operator Using Multiple Value Logic at 120 nm Technology. In: Satapathy, S., Bhateja, V., Joshi, A. (eds) Proceedings of the International Conference on Data Engineering and Communication Technology. Advances in Intelligent Systems and Computing, vol 469. Springer, Singapore. https://doi.org/10.1007/978-981-10-1678-3_30
Download citation
DOI: https://doi.org/10.1007/978-981-10-1678-3_30
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-1677-6
Online ISBN: 978-981-10-1678-3
eBook Packages: EngineeringEngineering (R0)