High Level Synthesis for Symmetric Key Cryptography

  • Ayesha KhalidEmail author
  • Goutam Paul
  • Anupam Chattopadhyay
Part of the Computer Architecture and Design Methodologies book series (CADM)


Classification of the major cryptographic functions on the basis of their under-lying basic computational elements yields simplicity and scalability in the design of cryptographic embedded systems. Especially, it benefits their high level synthesis, with performance as good as the hand crafted designs. This chapter discusses the various steps in the HLS tool for block ciphers (called RunFein) and stream ciphers (called RunStream). Several design points in the scope of architectural customizations available to the HLS tool are elaborated. A thorough benchmarking to compare against the hand crafted solutions reveals their performance to be at-par with hand-optimized HDL implementations. The results can be accessed as [1, 2, 3].


  1. 1.
    Khalid A, Hassan M, Chattopadhyay A, Paul G (2013) RAPID-FeinSPN: a rapid prototyping framework for Feistel and SPN-based block ciphers. In: International conference on information systems security (ICISS). Springer, Berlin, pp 169–190Google Scholar
  2. 2.
    Khalid A, Hassan M, Paul G, Chattopadhyay A (2016) RunFein: a rapid prototyping framework for Feistel and SPN-based block ciphers. J Cryptogr Eng 6(4):299–323Google Scholar
  3. 3.
    Khalid A, Paul G, Chattopadhyay A, Abediostad F, Din SIU, Hassan M, Biswas B, Ravi P (2016) RunStream: a high-level rapid prototyping framework for stream ciphers. ACM Trans Embed Comput Syst (TECS) 15(3):61Google Scholar
  4. 4.
    Rukhin A, Soto J, Nechvatal J, Smid M, Barker E (2001) A statistical test suite for random and pseudorandom number generators for cryptographic applications. NIST Special Publication 800-22, DTIC Document, Technical reportGoogle Scholar
  5. 5.
    Aysu A, Gulcan E, Schaumont P (2014) SIMON says: break area records of block ciphers on FPGAs. IEEE Embed Syst Lett 6(2):37–40Google Scholar
  6. 6.
  7. 7.
    Klose D, PRESENT C implementation (32 bit).
  8. 8.
    O Cores, Simple AES (Rijndael) IP core.,aes_core
  9. 9.
    Satoh A, Morioka S, Takano K, Munetoh S (2001) A compact Rijndael hardware architecture with S-box optimization. In: Advances in cryptology—ASIACRYPT. Springer, Berlin, pp 239–254Google Scholar
  10. 10.
    Rolfes C, Poschmann A, Leander G, Paar C (2008) Ultra-lightweight implementations for smart devices–security for 1000 gate equivalents. In: Smart card research and advanced applications. Springer, Berlin, pp 89–103Google Scholar
  11. 11.
    3rd Generation Partnership Project (2006) Specification of the 3GPP confidentiality and integrity algorithms UEA2 and UIA2. Document 1: UEA2 and UIA2 specification version 1.1, September 2006Google Scholar
  12. 12.
    Schneier B (1996) Applied cryptography. Wiley, New York, pp 397–398Google Scholar
  13. 13.
    OpenCores-RC4 (2013) OpenCores: RC4 pseudo-random stream generator.,rc4-prbs
  14. 14.
    Gaj K, Southern G, Bachimanchi R (2007) Comparison of hardware performance of selected phase II eSTREAM candidates. In: State of the art of stream ciphers workshop (SASC), vol 26Google Scholar
  15. 15.
    Traboulsi S, Pohl N, Hausner J, Bilgic A, Frascolla V (2012) Power analysis and optimization of the ZUC stream cipher for LTE-advanced mobile terminals. In: Third Latin American symposium on circuits and systems (LASCAS). IEEE, pp 1–4Google Scholar
  16. 16.
    ET Inc. (2011) CLP-410: ZUC key stream generator.
  17. 17.
    IC Inc. (2011) SNOW 3G encryption core.
  18. 18.
    Good T, Benaissa M (2008) ASIC hardware performance. In: New stream cipher designs. Springer, Berlin, pp 267–293Google Scholar
  19. 19.
    Galanis MD, Kitsos P, Kostopoulos G, Sklavos N, Koufopavlou O, Goutis CE (2004) Comparison of the hardware architectures and FPGA implementations of stream ciphers. In: 11th IEEE international conference on electronics, circuits and systems (ICECS). IEEE, pp 571–574Google Scholar
  20. 20.
    Good T, Chelton W, Benaissa M (2006) Review of stream cipher candidates from a low resource hardware perspective. In: SASC 2006 stream ciphers revisited, p 125Google Scholar
  21. 21.
    Good T, Benaissa M (2007) Hardware results for selected stream cipher candidates. In: State of the art of stream ciphers, pp 191–204Google Scholar
  22. 22.
    Good T, Benaissa M (2008) Hardware performance of eSTREAM phase-III stream cipher candidates. In: Workshop on the state of the art of stream ciphers (SACS)Google Scholar

Copyright information

© Springer Nature Singapore Pte Ltd 2019

Authors and Affiliations

  • Ayesha Khalid
    • 1
    Email author
  • Goutam Paul
    • 2
  • Anupam Chattopadhyay
    • 3
  1. 1.The Institute of Electronics, Communications and Information TechnologyQueen’s University BelfastBelfastIreland
  2. 2.Cryptology and Security Research Unit, R. C. Bose Centre for Cryptology and SecurityIndian Statistical InstituteKolkataIndia
  3. 3.School of Computer EngineeringNanyang Technological UniversitySingaporeSingapore

Personalised recommendations