Abstract
An energy efficient modified architecture of 8-bit 100 kS/s SAR ADC for the biomedical implant pacemaker is presented in this paper. With the stringent need to prolong the battery life of portable battery operated biomedical implants such as pacemaker, an improved architecture of SAR ADC is proposed which ensures improved performance than other reported SAR ADC architectures. The ADC employed in the pacemaker drains huge amount of power from battery during the time of analog to digital signal conversion. The work presents ADC design which ensures the microwatt operation which in turn makes the pacemaker to run on small battery. The ADC is realized in 180 nm CMOS technology operated at 1.8 V. The power consumption and energy efficiency reported during simulation are 2.5 µW and 0.77 pJ/state having precision of 6.68 bits.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Shouli Yan and Edgar Sanchez-Sinencio: Low Voltage Analog Circuit Design Techniques: A Tutorial, IEICE Transactions on Analog Integrated Circuits and Systems, vol. E00-A, no. 2, February (2000).
Philip E Allen & Douglas R Holberg: CMOS Analog Circuit Design, ISBN 0-19-511644-5, Oxford University Press, 2nd Edition, 2002.
Jens Sauerbrey, Doris Schmitt-Landsiedel, Roland Thewes: A 0.5 V, 1 μW Successive Approximation ADC, IEEE Journal of Solid State Circuit (2002).
Sandro A.P Haddad, Richard Houben and Wouter A. Serjdin: The evolution of pacemaker: an electronics perspective, from hand crank to advanced wavelet analysis, DISens symposium-book, 2005.
Kuttner, A. S. T. H. F., Sandner, C., & Clara, M.: A 6 bit, 1.2 gsps low-power flash-adc in 0.13 μm digital cmos, IEEE Journal of Solid-State Circuits Vol. 40, No. 7., 2005.
Deguchi, K., Suwa, N., Ito, M., Kumamoto, T., & Miki, T.: A 6-bit 3.5-GS/s 0.9-V 98-mW flash ADC in 90-nm CMOS. IEEE Journal of Solid-State Circuits, Vol. 43, No. 10, pp 2303–2310., 2008.
Chen, Fred, Anantha P. Chandrakasan, and Vladimir Stojanovic: A Low-power Area-efficient Switching Scheme for Charge sharing DACs in SAR ADCs, IEEE (2010).
G.Bonfini, C.Garbossa, R.Saletti, “A Switched OPAMP-based 10-bit Integrated ADC for Ultra Low-power Applications”, Via Giuntini 13, I-56023 Navacchio (Pi), Italy (2011).
RVNR Suneel Krishna, Aleti Shankar: Design of Low Power SAR-ADC in 0.18 μm, Mixed-Mode CMOS Process (2013).
Gulrej Ahmed and Rajendra Kumar Baghel: Design of 6-bit flash ADC converter using variable switching voltage CMOS comparator, VLSICS, Vol. 5, No. 3 (2014).
Akhil A, Sunil Jacob: Design of 9 bit SAR ADC using high speed and high resolution open loop CMOS comparator in 180 nm technology with R-2R DAC topology, International Journal of VLSI and Embedded Systems-IJVES, Vol. 05, Article 11492 (2014).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media Singapore
About this paper
Cite this paper
Jubin Jain, Maurya, V.K., Laskar, R.H., Rajeev Mathur (2016). Modified Design of Integrated Ultra Low Power 8-Bit SAR ADC Architecture Proposed for Biomedical Engineering (Pacemaker). In: Satapathy, S., Bhatt, Y., Joshi, A., Mishra, D. (eds) Proceedings of the International Congress on Information and Communication Technology. Advances in Intelligent Systems and Computing, vol 439. Springer, Singapore. https://doi.org/10.1007/978-981-10-0755-2_5
Download citation
DOI: https://doi.org/10.1007/978-981-10-0755-2_5
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-0754-5
Online ISBN: 978-981-10-0755-2
eBook Packages: EngineeringEngineering (R0)