Abstract
Application-specific integrated circuits (ASICs) are specialized custom-designed circuits which are developed to carry out desired tasks efficiently in hardware. Often, microprocessors are preferred over ASICs , since they give flexibility to users. They allow the same hardware to be used for a variety of applications. Still for applications requiring very high speed computation and/or very low energy ASICs have been preferred over software solutions. Microprocessors are typically based on Von Neumann architecture , which allow execution of stored programs (Von Neumann, IEEE Ann. Hist. Comput. 15(4): 27–75, 1993). For implementing a specific application, the user writes software programs to specify the sequence of tasks that gets executed within the processor. Rapid advances in VLSI technology have enabled fabrication of billions of transistors on a single chip. Technology scaling has allowed number of transistors to double every 18 months in accordance to Moore’s law (Moore, Prod. IEEE 86(1):82–85, 1998). This technological advancement has led to design and development of faster and energy-efficient hardware. Availability of faster processors enabled software based solutions to replace hardware solutions over increasingly larger domain. In the past few years, frequency scaling of processors has saturated due to thermal limitations and the integrated circuit (IC) designers are focusing on gaining speedups by running more operations concurrently in hardware; either on multi-core processors or on specialized hardware.
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Notes
- 1.
The protein structures are denoted by their four letter code in the Protein Data Bank.
References
Moore, G.: Cramming more components onto integrated circuits. Proc. IEEE 86(1), 82–85 (1998)
Von Neumann, J.: First draft of a report on the EDVAC. IEEE Ann. Hist. Comput. 15(4), 27–75 (1993)
Stone, J., Gohara, D., Shi, G.: Opencl: a parallel programming standard for heterogeneous computing systems. Comput. Sci. Eng. 12(3), 66–73 (2010)
Che, S., Li, J., Sheaffer, J., Skadron, K., Lach, J.: Accelerating compute-intensive applications with GPUs and FPGAs. In: Symposium on Application Specific Processors, 2008. SASP 2008, pp. 101–107 (2008)
Chung, E., Milder, P., Hoe, J., Mai, K.: Single-chip heterogeneous computing: does the future include custom logic, FPGAs, and GPGPUs? In: Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2010)
Xilinx: Xilinx FPGAs, ISE. http://www.xilinx.com (2015)
Beauchamp, M.J., Hauck, S., Underwood, K.D., Hemmert, K.S.: Embedded floating-point units in FPGAs. In: ACM/SIGDA International Symposium on FPGAs (2006)
Yu, C.W., Smith, A., Luk, W., Leong, P., Wilton, S.: Optimizing coarse-grained units in floating point hybrid FPGA. In: International Conference on FPT (2008)
Jain, A., Gambhir, P., Jindal, P., Balakrishnan, M., Paul, K.: Fpga accelerator for protein structure prediction algorithm. In: 5th Southern Conference on Programmable Logic, 2009, SPL (2009)
Tang, W., Wang, W., Duan, B., Zhang, C., Tan, G., Zhang, P., Sun, N.: Accelerating millions of short reads mapping on a heterogeneous architecture with fpga accelerator. In: Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 184–187 (2012)
Zhu, T., Cao, S., Su, P.C., Patel, R., Shah, D., Chokshi, H.B., Szukala, R., Johnson, M.E., Hevener, K.E.: Hit identification and optimization in virtual screening: practical recommendations based on a critical literature analysis. J. Med. Chem. 56(17), 6560–6572 (2013)
Sternberg, M.J.E., Aloy, P., Gabb, H.A., Jackson, R.M., Moont, G., Querol, E., Aviles, F.X.: A computational system for modeling flexible protein-protein and protein-DNA docking. In: Proceedings of the 6th International Conference on Intelligent Systems for Molecular Biology, pp. 183–192 (1998)
Frigo, M., Johnson, S.G.: The design and implementation of FFTW3. In: Proceedings of the IEEE (2005)
Ayman, G., Kate, W.: Next-generation sequencing: methodology and application. J. Invest. Dermatol. 133 (2008)
Liu, Y., Schmidt, B., Maskell, D.: Parallelized short read assembly of large genomes using de Bruijn graphs. BMC Bioinform. 12(1), 354–363 (2011)
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Varma, B.S.C., Paul, K., Balakrishnan, M. (2016). Introduction. In: Architecture Exploration of FPGA Based Accelerators for BioInformatics Applications. Springer Series in Advanced Microelectronics, vol 55. Springer, Singapore. https://doi.org/10.1007/978-981-10-0591-6_1
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