Abstract
In this paper, 28T CNFET-based full adder circuit is proposed. With the increase in the number of transistors and speed per unit chip area, power consumption of VLSI circuits has also increased. Power has become an extremely important design constraint along with the area and speed in modern VLSI design. So, carbon nanotubes with their superior properties, high current drivability, and high thermal conductivities have emerged as potential alternative devices to the CMOS technology. In this paper, average power consumption, energy and delay of Si MOSFET and CNFET-based full adder have been analyzed. The simulation was carried out using HSPICE circuit simulator. The simulation results show that power consumption, energy, and PDP of CNFET-based full adder is 56, 54.74, and 59 % reduced, respectively, in comparison to the Si MOSFET-based full adder. Moreover, the delay is also reduced approx by 8.69 % for sum output and 8.63 % for carry output.
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References
Soni, G.: Performance evaluation of carbon nanotube based devices and circuits for VLSI design. M.Tech. Thesis, Department of Electronics and Communication Engineering, Malaviya National Institute of Technology Jaipur, June 2013
Deng, J.: Device modeling and circuit performance evaluation for nanoscale devices: silicon technology beyond 45 nm node and carbon nanotube field effect transistors. Ph.D. thesis, Department of Electrical Engineering, Stanford University, Stanford (2007)
Sethi, R., Soni, G.: Power analysis of Si MOSFET and CNFET based logic gates. Int. J. Eng. Manag. Sci. (Alied Journals-IJEMS) 2(5) (2015) ISSN-2348–3733
Saha, P.: Noise margin modeling and performance analysis of CNFET based SRAM. M.Tech. Thesis, Department of Electronics and Telecommunication Engineering, Jadavpur University (2013)
Shahidipour, H.: A study on the effects of variability on performance of CNFET based digital circuits, Ph.D. thesis, School of Electronics and Computer Science, University of Southampton, Mar, 2012
Kang, S.M., Leblebici, Y.: Cmos Digital Integrated Circuits: Analysis and Design, 3rd edn. Tata McGraw Hill, 2003
Gaur, S., Soni, G., Kumari, S.S.: Power and delay optimization of 1 bit full adder using MTCMOS technique. In: International Conference on Advances in Engineering and Technology—ICAET (2014)
Dhilleswararao, P., Mahapatra, R., Srinivas, P.S.T.N.: High SNM 32 nm CNFET based 6T SRAM cell design considering transistor ratio. In: 2014 International Conference on Electronics and Communication Systems (ICECS), pp. 1, 6, 13–14 Feb 2014
Shi, F., Wu, X., Yan, Z.: Improved analytical delay models for RC-coupled interconnects. In: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 22(7), 1639, 1644 (2014)
Cho, G., Kim, Y.-B., Lombardi, F., Choi, M.: Performance evaluation of CNFET-based logic gates. In: Instrumentation and Measurement Technology Conference, 2009. I2MTC ‘09. IEEE, pp. 909, 912, 5–7 May 2009
Halder, A., Maheshwari, V., Goyal, A., Kar, R., Mandal, D., Bhattacharjee, A.K.: Moment based delay modelling for on-chip RC global VLSI interconnect for unit ramp input. In: 2012 International Joint Conference on Computer Science and Software Engineering (JCSSE), pp. 164, 167, 30 May 2012–1 June 2012
http://www.itrs.net/Links/2011ITRS/2011Chapters/2011SysDrivers.pdf
Shin, J.Y., Dutt, N., Kurdahi, F.: Vision-inspired global routing for enhanced performance and reliability. In: 2013 14th International Symposium on Quality Electronic Design (ISQED), pp. 239, 244, 4–6 March 2013
Kavicharan, M., Murthy, N.S., Rao, N.B.: An efficient delay estimation model for high speed VLSI interconnects. In: 2013 International Conference on Advances in Computing, Communications and Informatics (ICACCI), pp. 1358, 1362, 22–25 Aug 2013
Seokjoong, K., Guthaus, M.R.: SNM-aware power reduction and reliability improvement in 45 nm SRAMs. In: IEEE/IFIP 19th International Conference on VLSI and System-on-Chip (VLSI-SoC), 2011, pp. 204, 207, 3–5 Oct 2011
Lamberti, P., Tucci, V.: Impact of the variability of the process parameters on CNT-based nanointerconnects performances: a comparison between SWCNTs bundles and MWCNT. IEEE Trans. Nanotechnol. 11(5), 924–933, (2012)
Sun, L., Mathew, J., Shafik, R.A., Pradhan, D.K., Li, Z.: A low power and robust carbon nanotube 6T SRAM design with metallic tolerance. In: Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014, pp. 1, 4, 24–28 March 2014
Maheshwari, V., Agarwal, S., Goyal, A., Jain, J., Kumar, S., Kar, R., Mandal, D., Bhattacharjee, A.K.: Elmore’s approximations based explicit delay and rise time model for distributed RLC on-chip VLSI global interconnect. In: 2012 IEEE Symposium on Humanities, Science and Engineering Research (SHUSER), pp. 1135, 1139, 24–27 June 2012
Maheshwari, V., Baboo, A., Kumar, B., Kar, R., Mandal, D., Bhattacharjee, A.K.: Delay model for VLSI RLCG global interconnects line. In: 2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), pp. 201, 204, 5–7 Dec 2012
Majumder, M.K., Das, P.K., Kaushik, B.K., Manhas, S.K.: Optimized delay and power performances for multi-walled CNT in global VLSI interconnects. In: 2012 5th International Conference on Computers and Devices for Communication (CODEC), pp. 1, 4, 17–19 Dec 2012
Majumder, M.K., Pandya, N.D., Kaushik, B.K., Manhas, S.K.: Analysis of MWCNT and Bundled SWCNT Interconnects: Impact on Crosstalk and Area. IEEE Electron Device Lett. 33(8), pp. 1180, 1182, Aug 2012
Mehran, M., Masoumi, N.: A tapered partitioning method for “delay energy product” optimization in global interconnects. In: 50th Midwest Symposium on Circuits and Systems, 2007. MWSCAS 2007, pp. 21, 24, 5–8 Aug 2007
Moradi, M., Mirzaee, R.F., Moaiyeri, M.H., Navi, K.: An applicable high-efficient CNTFET-based full adder cell for practical environments. In: 2012 16th CSI International Symposium on Computer Architecture and Digital Systems (CADS), pp. 7, 12, 2–3 May 2012
Somorjit Singh, N., Madheswaran, M.: Simulation and analysis of 3t and 4t cntfet dram design in 32 nm technology. Int. J. Electron. Sign. Syst. (IJESS) 3, 59–65 (2013) ISSN: 22315969
Pushkarna, A., Raghavan, S., Mahmoodi, H.: Comparison of performance parameters of SRAM designs in 16 nm CMOS and CNTFET technologies. In: 2010 IEEE International SOC Conference (SOCC), pp. 339, 342, 27–29 Sept 2010
Prasad, S.R., Madhavi, B.K., Kishore, K.L.: Design of a 32 nm 7T SRAM Cell based on CNTFET for low power operation. In: 2012 International Conference on Devices, Circuits and Systems (ICDCS), pp. 443, 446, 15–16 March 2012
Lin, S., Kim, Y.-B., Lombardi, F.: Design of a CNTFET-based SRAM cell by dual-chirality selection. IEEE Trans. Nanotechnol. 9(1), 30, 37, (2010)
Kim, Y.B., Kim, Y.-B., Lombardi, F., Lee, Y.J.: A low power 8T SRAM cell design technique for CNFET. In: International SoC Design Conference, 2008. ISOCC ‘08. vol. 01, pp. I–176, 24–25 Nov 2008
Kim, Y.B.: Design methodology based on carbon nanotube field effect transistor (CNFET), Ph.D. thesis, Department of Electrical and Computer Engineering, Northeastern University Boston, Massachusetts, Jan 2011
Zhang, Z., Delgado-Frias, J.G.: Low power and metallic CNT tolerant CNTFET SRAM design. In: 2011 11th IEEE Conference on Nanotechnology (IEEE-NANO), pp. 1177, 1182, 15–18 Aug 2011
Zhang, Z., Delgado-Frias, J.G., CNTFET SRAM cell with tolerance to removed metallic CNTs. In: 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 186, 189, 5–8 Aug 2012
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Rishika Sethi, Gaurav Soni (2016). Comparative Analysis of Si-MOSFET and CNFET-Based 28T Full Adder. In: Pant, M., Deep, K., Bansal, J., Nagar, A., Das, K. (eds) Proceedings of Fifth International Conference on Soft Computing for Problem Solving. Advances in Intelligent Systems and Computing, vol 436. Springer, Singapore. https://doi.org/10.1007/978-981-10-0448-3_36
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DOI: https://doi.org/10.1007/978-981-10-0448-3_36
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