Abstract
With the dramatic increase of circuit scale and the harsh environment, the reliability of the system has become the great hidden danger. Triple different-structure modular redundant system based on evolution mechanism shows good fault tolerant ability. How to enhance the efficiency and diversity of the evolution generation module has become the key issue which can ensure the system fault tolerant. This article puts forward two-stage mutation evolution strategy (TMES) and interactive two-stage mutation evolution strategy (ITMES) based on improving virtual reconfigurable architecture platform to evolve combination logical circuit on the fault-tolerant system with different-structure redundancy module. The efficiency of the proposed methodology is tested with the evolutions of a 2-bit multipliers, and a 3-bit multipliers, and a 3-bit full adders. The obtained results demonstrate the effectiveness of the scheme on generation circuit diversity and evolution efficiency.
Foundation item: Projects (HBSKFMS2014009) supported by the Hubei Collaborative Innovation Center for High-efficient Utilization of Solar Energy.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Rollins, N., Wirthlin, M., Caffrey, M., et al.: Evaluating TMR techniques in the presence of single event upsets. In: Proceedings of the Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Washington, DC, p. 63 (2003)
Carmichael, C.: Triple module redundancy design techniques for virtex FPGAs. xAPPl97(v1.0). Xilinx Corp., San Jose (2001)
Ping, J., Wang, Y., Kong, D., Yao, R.: Research on technology of different-structure system based on evolvable hardware. J. Chin. Compute Syst. 30(11), 2290–2293 (2009)
Pratt, B., Caffrey, M., Carroll, J.F., et al.: Fine-grain SEU mitigation for FPGAs using partial TMR. IEEE Trans. Nucl. Sci. 55(4), 2274–2280 (2008)
Lin, Y., Luo, W., Wang, X.: The selective evolution redundancy of hardware circuit. J. USTC 36(5), 523–529 (2006)
Higuchi, T., Iwata, M., Keymeulen, D., Sakanashi, H., et al.: Real-world applications of analog and digital evolvable hardware. IEEE Trans. Evol. Comput. 3(3), 220–235 (1999)
Gao, G.J., Wang, Y.R., Yao, R.: Research on redundancy and tolerance of system with different structures. Transducer Microsyst. Technol. 26(10), 25–28 (2007)
Yao, R., Wang, Y., Yu, S., Cheng, Z.: Design and experiments of enhanced fault–tolerant triple-module redundancy systems capable of online self-repairing. Acta Electro. Sin. 38(1), 177–183 (2010)
Sekanina, L.: Virtual reconfigurable circuits for real-world applications of evolvable hardware. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds.) ICES 2003. LNCS, vol. 2606, pp. 186–197. Springer, Heidelberg (2003)
Glette, K., Torresen, J.: A flexible on-chip evolution system implemented on a Xilinx virtex-II pro device. In: Moreno, J., Madrenas, J., Cosp, J. (eds.) ICES 2005. LNCS, vol. 3637, pp. 66–75. Springer, Heidelberg (2005)
Wang, J., Chen, Q.S., Lee, C.H.: Design and implementation of a virtual reconfigurable architecture for different applications of intrinsic evolvable hardware. IET Comput. Digital Tech. 2(5), 386–400 (2008)
Li, K., Liang, J., Zhang, W., et al.: Optimization algorithm for complicated circuit based on GEP. Comput. Eng. Appl. 44(18), 83–86 (2008)
Miller, J.F., Thomson, P.: Cartesian genetic programming. In: Banzhaf, W., Fogarty, T.C., Langdon, W.B., Miller, J., Nordin, P., Poli, R. (eds.) EuroGP 2000. LNCS, vol. 1802, pp. 121–132. Springer, Heidelberg (2000)
Oltean, M., Grosan, C.: Evolving digital circuits using multi expression programming. In: Proceedings of the 2004 NASA/DoD Conference on Evolution Hardware (EH2004) (2004)
Miller, J.F., Smith, S.L.: Redundancy and computational efficiency in Cartesian genetic programming. IEEE Trans. Evol. Comput. 10(2), 167–174 (2006)
Vassilev, V.K., Miller, J.F.: The advantages of landscape neutrality in digital circuit evolution. In: Miller, J.F., Thompson, A., Thompson, P., Fogarty, T.C. (eds.) ICES 2000. LNCS, vol. 1801, pp. 252–263. Springer, Heidelberg (2000)
Vassilev, V.K., Miller, J.F.: Scalability problems of digital circuit evolution evolvability and efficient designs. In: Proceedings of the Second Conference on Evolvable Hardware (2000)
Gordon, T.G.W., Bentley, P.J.: Towards development in evolvable hardware. In: Proceedings of the 2002 NASA/DOD Conference on Evolvable Hardware (EH 2002), pp. 241–250 (2002)
Lee, J., Sitte, J.: Issues in the scalability of gate-level morphogenetic evolvable hardware. In: Recent Advances in Artificial Life, Advances in Natural Computation, vol. 3, pp. 145–158. World Scientific, Singapore (2005)
Tufte, G.: Discovery and investigation of inherent scalability in developmental genomes. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds.) ICES 2008. LNCS, vol. 5216, pp. 189–200. Springer, Heidelberg (2008)
Wang, J., Lee, C.H.: Virtual reconfigurable architecture for evolving combinational logic circuits. J. Cent. South. Univ. 21, 1862–1870 (2014)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media Singapore
About this paper
Cite this paper
Yang, X., Li, Y., Fang, C., Nie, C., Ni, F. (2016). Research on Evolution Mechanism in Different-Structure Module Redundancy Fault-Tolerant System. In: Li, K., Li, J., Liu, Y., Castiglione, A. (eds) Computational Intelligence and Intelligent Systems. ISICA 2015. Communications in Computer and Information Science, vol 575. Springer, Singapore. https://doi.org/10.1007/978-981-10-0356-1_17
Download citation
DOI: https://doi.org/10.1007/978-981-10-0356-1_17
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-10-0355-4
Online ISBN: 978-981-10-0356-1
eBook Packages: Computer ScienceComputer Science (R0)