Abstract
In the recent RISC processor the floating-point ALU unit plays a vital role in performing the floating-point arithmetic operations. The 8-bit floating point is represented using the IEEE 754 format. This paper presents the architectural design of an 8-bit floating-point synchronous adder and subtractor unit. In a synchronous system the execution is performed with respect to the clock and the speed of execution is improved by a pipelining process. The architecture of a floating-point synchronous adder and subtractor unit has been designed and the performances analyzed in the Xilinx environment.
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Ravi, T. (2016). Architectural Design of 8-Bit Floating-Point Synchronous Adder and Subtractor for RISC ALU. In: Shetty, N., Prasad, N., Nalini, N. (eds) Emerging Research in Computing, Information, Communication and Applications . Springer, Singapore. https://doi.org/10.1007/978-981-10-0287-8_21
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DOI: https://doi.org/10.1007/978-981-10-0287-8_21
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