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Comparative Analysis of Different Architectures of MCML Square Root Carry Select Adders for Low-Power Applications

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Proceedings of International Conference on ICT for Sustainable Development

Part of the book series: Advances in Intelligent Systems and Computing ((AISC,volume 409))

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Abstract

In digital electronics, adders are the most widely used circuits in order to perform fast arithmetic operations. Square root carry select adder is the fastest adder used in various digital processors. This paper presents the comparative analysis of different architectures of MCML square root carry select adders. Comparison with MCML RCA is also given. It is seen that modified MOS current mode logic (MCML) square root carry select adder (MSQ-CSA) has reduced power and increased speed. Therefore, it can be used instead of regular SQ-CSA and MCML ripple carry adder in order to perform high-speed and low-power operations. The simulation is performed in T-SPICE using 16 nm technology parameters. It is found that the proposed MCML SQ-CSA is efficient in terms of power and delay in comparison to other MCML adders.

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References

  1. Rabaey, J. M. (2001). Digtal integrated circuits—a design perspective. Upper Saddle River, NJ: Prentice-Hall.

    Google Scholar 

  2. Agarwal, T. K., Sawhney, A., Kureshi, A. K., & Hasan, M.: Performance comparison of static CMOS and MCML gates in sub- threshold region of operation for 32 nm CMOS technology. In Proceedings of the International Conference on Computer and Communication Engineering (pp. 284–287). Malaysia, 2008.

    Google Scholar 

  3. Gupta, K., Pandey, N., & Gupta, M. (2010). A novel active shunt-peaked MCML-based high speed four-bit ripple-carry adder. In Proceedings of IEEE International Conference on Computer and Communication Technology (pp. 285–289).

    Google Scholar 

  4. Kim, J. B. (2009). Low-power MCML circuit with sleep-transistor. In IEEE Proceedings 2009.

    Google Scholar 

  5. Amer, S.H., Emara, A.S., Mohie El-Din, R., Fouad, M.M., Madian, A.H., Amer, H.H., Abdelhalim, M.B., & Draz, H.H. (2014). Testing current mode two- input logic gates. In IEEE CCECE 2014. Toronto, Canada.

    Google Scholar 

  6. Fouad, M., Amer, H. H., Madian, A. H., & Abdelhalim, M. B. (2013). Current mode logic testing of XOR/XNOR circuit: A case study. Circuits and Systems, Scientific Research Publishing, 4, 364–368.

    Article  Google Scholar 

  7. Gupta, K. Radhika, Pandey, N., & Gupt, M. (2013). A novel high speed MCML square root carry select adder for mixed signal applications. In IEEE IMPACT-2013.

    Google Scholar 

  8. Ramkumar, B., Kittur, H. M., & Kannan, P. M. (2010). ASIC implementation of modified faster carry save adder. European Journal of Scientific Research, 42(1), 53–58.

    Google Scholar 

  9. Kim, Y., & Kim, L. S. (2001). 64-bit carry select adder with reduced area. Electronics Letters, 37(10), 614–615.

    Article  Google Scholar 

  10. Ceiang, T. Y., & Hsiao, M. J. (1998). Carry–Select adder using single ripple carry adder. Electronics Letters, 34(2), 2101–2103.

    Google Scholar 

  11. Saxena, P., Purohit, U., & Joshi, P. (2013). Analysis of low power, area-efficient and high speed fast adder. International Journal of Advanced Research in Computer and Communication Engineering, 2(9), September 2013.

    Google Scholar 

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Correspondence to Ginni Jain .

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© 2016 Springer Science+Business Media Singapore

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Jain, G., Vyas, K., Maurya, V.K., Patel, M. (2016). Comparative Analysis of Different Architectures of MCML Square Root Carry Select Adders for Low-Power Applications. In: Satapathy, S., Joshi, A., Modi, N., Pathak, N. (eds) Proceedings of International Conference on ICT for Sustainable Development. Advances in Intelligent Systems and Computing, vol 409. Springer, Singapore. https://doi.org/10.1007/978-981-10-0135-2_29

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  • DOI: https://doi.org/10.1007/978-981-10-0135-2_29

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-10-0133-8

  • Online ISBN: 978-981-10-0135-2

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