Bio-inspired Ultralow Power Design of Comparator with Noise Compensation Using Hysteresis Technique Designed for Biomedical Engineering (Pacemaker)

Abstract

With the emerging development of advanced trends in biomedical engineering finding its application in various biomedical electronic devices such as ECG, EEG, temperature sensing, blood pressure, and pacemaker, the biopotential signals are picked-up in small portable battery operated devices. The major concerned is about the power consumption of the electronic circuitry used in biomedical devices as well as the noise obtained from the muscular contraction and expansion, which is responsible for the interference to the signal to be measured. Hence, compensation circuitry is needed to remove noise. The comparator is a CMOS VLSI circuit which compares an analog signal with another analog signal and generates digital output due to comparison. The project is to show case the low power consumption of comparator proposed for pacemaker device having modest speed and producing less delay. The technique proposed to design the comparator in order to improve the performance is hysteresis by providing feedback. The advantage of introducing hysteresis in comparator is to compensate the noise at output signal, when operated in noisy environment. The comparator using hysteresis is designed in 0.18 μ CMOS technology operated at bias voltage of 1.8 V. The circuit is designed and simulated in TANNER EDA.