Abstract
Ferroelectric-gate field effect transistor (FeFET) memories are overviewed. The FeFET shows excellent features as an integrated memory such as nonvolatality, better scalability, higher read-write speeds, lower dissipation powers, higher tamper resistances and higher radioactivity tolerance. But, memory retention was the most critical problem for its practical realization. Mechanisms of degradation of the retention are discussed in metal-ferroelectric-insulator-semiconductor (MFIS) gate structure in which the insulator is inserted between the ferroelectric and the semiconductor to avoid interface damages suffered during the device preparation at high temperature. It is concluded from careful discussion that leakage currents through insulator-semiconductor and metal-ferroelectric junctions store charges in the interface between the ferroelectric and the insulator layers, which reduce apparent dielectric polarization and promote the degradation of the retention. Electronic property of the interfaces and the ferroelectric layer in the MFIS structure has been improved by nitrogen radical treatment and thermal annealing, and the retention of MFIS capacitance is shown to extend very much. Moreover, several kinds of improved MFIS FETs are introduced and the memory retention has been extended very much to be useful for the practical realization of excellent memory devices.
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Acknowledgments
The author would like to thank Dr. Mitsue Takahashi and Profs. Minoru Noda and Takeshi Kanashima for helping this work, and Enago (www.enago.jp) for the English language review.
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Okuyama, M. (2016). Features, Principles and Development of Ferroelectric–Gate Field-Effect Transistors. In: Park, BE., Ishiwara, H., Okuyama, M., Sakai, S., Yoon, SM. (eds) Ferroelectric-Gate Field Effect Transistor Memories. Topics in Applied Physics, vol 131. Springer, Dordrecht. https://doi.org/10.1007/978-94-024-0841-6_1
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