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Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting pp 33–64Cite as

Bulk FinFETs: Design at 14 nm Node and Key Characteristics

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Abstract

In contrast to conventional 2-D MOSFETs, FinFETs are able to be scaled down to 20 nm and beyond, and have superior performance. There are two types of FinFETs:SOI FinFETs and bulk FinFETs. Bulk FinFETs are built on bulk-Si wafers, which have less defect density and are cheaper than SOI wafers, while also having better heat transfer rate to the substrate compared to SOI FinFETs. In 2011, Intel announced the world’s first 3-D transistors in the mass production of a 22 nm microprocessor (code-named Ivy Bridge). The 3-D transistors adopted by Intel are actually bulk FinFETs. In this chapter, we provide the design guidelines for bulk FinFETs at the 14 nm node, and compare bulk and SOI FinFETs in terms of scalability, parasitic capacitance, and heat dissipation. Decrease of the drain current by parasitic resistance in the source (S) and drain (D) regions is also addressed. Drain current fluctuation by single charge trap is studied in terms of the trap depth, trap position, and percolation path. In the design of 14 nm bulk FinFETs, a punch-through stopper at a position just under the S/D junction depth is required to suppress unwanted cross-talk between S and D. The peak concentration of the stopper needs to be 2–3 × 1018 cm−3. The S/D junction depth should be equal or slightly smaller than the height of fin body, defined from the surface of the isolation oxide region to the top of the fin body. Considering the short channel effect and drain current drivability, the reasonable doping concentration of uniformly doped fin body is 2–3 × 1017 cm−3. To keep the drain-induced barrier below 100 mV/V when the length between the S and D junctions is the same as the gate length (14 nm), the width of the fin body should be ~9 nm. Under the same doping concentration and geometry, both 14 nm SOI and bulk FinFETs have nearly the same I–V characteristics, which mean nearly the same scalability. Since thin fin bodies protruding from the substrate are easily depleted, the junction capacitance of the S/D to fin body can be reduced to similar or even lower values than that of SOI FinFETs. To achieve a similar heat transfer rate to the substrate as bulk FinFETs, the buried oxide in SOI FinFETs should be thinned down to 20 nm or beyond, which could cause unwanted increase in the parasitic capacitance. The contact area between the metal electrode and the S/D region should be as wide as possible to reduce the S/D parasitic resistance.

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Acknowledgments

This work was supported by the Center for Integrated Smart Sensors, funded by the Ministry of Science, ICT & Future Planning, as the Global Frontier Project.

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  1. School of ECE, Seoul National University, 1 Gwanak-ro, Gwanak-gu, Seoul, 151-742, Korea

    Jong-Ho Lee

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  1. Electrical Engineering Center for Integrated Smart Sensors, KAIST, Daejoen, Korea, Republic of (South Korea)

    Chong-Min Kyung

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Lee, JH. (2016). Bulk FinFETs: Design at 14 nm Node and Key Characteristics. In: Kyung, CM. (eds) Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting. KAIST Research Series. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9990-4_2

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