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Tunneling Field-Effect Transistors for Ultra-Low-Power Application

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Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting

Part of the book series: KAIST Research Series ((KAISTRS))

Abstract

One of the major roadblocks to further scaling of complementary metal-oxide semiconductor (CMOS) devices is power consumption. Reduction of power consumption requires low operation voltage, which requires low threshold voltage. In order to decrease the threshold voltage without excessive increase of OFF current, reduction of the subthreshold swing is essential. To reduce the subthreshold swing, various carrier injection mechanisms other than thermal carrier injection have been proposed. Currently, interband tunneling is the most promising mechanism and the device that utilizes such a mechanism is a tunneling field-effect transistor (TFET). After the introduction to the fundamentals of TFETs, various approaches to increase the drain current of Si TFETs by device structure engineering are described. The last section focuses on bandgap engineering to enhance the drain current of TFETs.

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References

  1. ITRS Committee (2013) International technology roadmap for semiconductors. http://public.itrs.net/

  2. Gopalakrishnan K, Griffin PB, Plummer JD (2002) I-MOS: A novel semiconductor device with a subthreshold slope lower than kT/q. In: IEDM Technical Digest, p 289

    Google Scholar 

  3. Gopalakrishnan K, Griffin PB, Plummer JD (2005) Impact ionization MOS (I-MOS)-part I: device and circuit simulations. IEEE Trans. Electron Dev 52:69

    Article  Google Scholar 

  4. Gopalakrishnan K, Woo R, Jungemann C, Griffin PB, Plummer JD (2005) Impact ionization MOS (I-MOS)-part II: experimental results. IEEE Trans. Electron Dev 52:77

    Article  Google Scholar 

  5. Choi WY, Song JY, Lee JD, Park YJ, Park B-G (2005) A novel biasing scheme for I-MOS (impact-ionization MOS) devices. IEEE Trans Nanotechnol 4:322

    Article  Google Scholar 

  6. Choi WY, Song JY, Lee JD, Park YJ, Park BG (2005) 70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs). In: IEDM Technical Digest, p 975

    Google Scholar 

  7. Kinaret J, Nord T, Viefers S (2003) A carbon-nanotube-based nanorelay. Appl Phys Lett 82:1287

    Article  Google Scholar 

  8. Kam H, Lee DT, Howe RT, King T-J (2005) A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics. In: IEDM Technical Digest, p 463

    Google Scholar 

  9. Abele N, Fritschi N, Boucart K, Casset F, Ancey P, Ionescu AM (2005) Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor. In: IEDM Technical Digest, p 1075

    Google Scholar 

  10. Yousif M, Lundgren P, Ghavanini F, Enoksson P, Bengtsson S (2008) CMOS considerations in nanoelectromechanical carbon nanotube-based switches. Nanotechnology 19:285204

    Article  Google Scholar 

  11. Loh OY, Espinosa HD (2012) Nanoelectromechanical contact switches. Nature Nanotechnol 7:283

    Article  Google Scholar 

  12. Appenzeller J, Lin Y-M, Knoch J, Avouris P (2004) Band-to-band tunneling in carbon nanotube field-effect transistors. Phys Rev Lett 93:196805

    Article  Google Scholar 

  13. Bhuwalka KK, Schulze J, Eisele I (2004) Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer. Jpn J Appl Phys 43:4073

    Article  Google Scholar 

  14. Zhang Q, Shao W, Seabaugh A (2006) Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett 27:297

    Article  Google Scholar 

  15. Nirschl T, Weis M, Fulde M, Schmitt-Landsiedel D (2007) Correction to revision of tunneling field-effect transistor in standard CMOS technologies. IEEE Electron Device Lett 28:315

    Article  Google Scholar 

  16. Choi WY, Park B-G, Lee JD, King Liu T-J (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec. IEEE Electron Device Lett 28(8):743

    Article  Google Scholar 

  17. Fair RB, Wivell HW (1976) Zener and avalanche breakdown in As-implanted low voltage Si n-p junctions. IEEE Trans Electron Devices 23:512

    Article  Google Scholar 

  18. Vallett AL, Minassian S, Kaszuba P, Datta S, Redwing JM, Mayer HS (2010) Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors. Nano Lett 10:4813

    Article  Google Scholar 

  19. Chen ZX, Yu HY, Singh N, Shen NS, Sayanthan RD, Lo GQ, Kwong D-L (2009) Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires. IEEE Electron Device Lett 30(7):754

    Article  Google Scholar 

  20. Yang B, Buddharaju KD, Teo SHG, Singh N, Lo GQ, Kwong DL (2008) Vertical silicon-nanowire formation and gate-all-around MOSFET. IEEE Electron Device Lett 29(7):791

    Article  Google Scholar 

  21. Kwong D-L, Li X, Sun Y, Ramanathan G, Chen ZX, Wong SM, Li Y, Shen NS, Buddharaju K, Yu YH, Lee SJ, Singh N, Lo GQ (2012) Vertical silicon nanowire platform for low power electronics and clean energy applications. J Nanotechnol 2012:492121

    Article  Google Scholar 

  22. Lee M, Jeon Y, Jung J-C, Koo S-M, Kim S (2012) Multiple silicon nanowire complementary tunnel transistors for ultralow-power flexible logic applications. Appl Phys Lett 100:253506

    Article  Google Scholar 

  23. Park BG, Sun MC, Kim SW (2014) Silicon tunneling field effect transistors with a hemicylindrical nanowire channel for ultra-low power application. In: Conference Proceedings, 012021

    Google Scholar 

  24. Kim SW, Choi WY, Sun M-C, Kim HW, Park B-G (2012) Design guideline of Si-based L-shaped tunneling field-effect transistors. Japan J Appl Phys 51(06FE09)

    Google Scholar 

  25. A.S. Verhulst, William G. Vandenberghe, K. Maex, and G. Groeseneken, “Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization,” Journal of Applied Physics, 104, 064514 (2008)

    Google Scholar 

  26. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329

    Article  Google Scholar 

  27. Tomioka K, Fukui T (2011) Tunnel field-effect transistor using InAs nanowire/Si heterojunction. Appl Phys Lett 98:083114

    Article  Google Scholar 

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Acknowledgments

This work is supported by the Center for Integrated Smart Sensors funded by the Ministry of Science, ICT and Future Planning as the Global Frontier Project.

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Authors and Affiliations

  1. Seoul National University, Seoul, Korea

    Byung-Gook Park

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  1. Byung-Gook Park
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Correspondence to Byung-Gook Park .

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Editors and Affiliations

  1. Electrical Engineering Center for Integrated Smart Sensors, KAIST, Daejoen, Korea, Republic of (South Korea)

    Chong-Min Kyung

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Park, BG. (2016). Tunneling Field-Effect Transistors for Ultra-Low-Power Application. In: Kyung, CM. (eds) Nano Devices and Circuit Techniques for Low-Energy Applications and Energy Harvesting. KAIST Research Series. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9990-4_1

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  • DOI: https://doi.org/10.1007/978-94-017-9990-4_1

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-017-9989-8

  • Online ISBN: 978-94-017-9990-4

  • eBook Packages: EngineeringEngineering (R0)

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