Abstract
This paper presents CMOS integrated electrical over stress (EOS) protection circuit for USB2 transceiver. A unique full speed SE0 state in USB2 standard protocol produces overshoot and undershoots in presence of an on board choke. The purpose of choke is to minimize EMI for USB2 differential signaling. This works fine as long as data signaling is differential. In the presence of SE0 state, single transition occurs on either Dp or Dn pad causing high inductive kick back from choke resulting in excessive overshoot and undershoots. The electrical over stress on cascode devices leads to device degradation resulting in violation of USB2 output driver impedance spec of 45 Ω ±5 %. This in turn increases ‘defects per million’ count over time. To mitigate this reliability issue, EOS protection circuit is proposed. This circuit is designed in Intel-22 nm process and evaluated by computer simulations across all PVT conditions. Proposed EOS protection circuit reduces respective overshoot and undershoot of 4.2 V and −0.6 to 3.7 V and −0.34 V. For the growing EOS concern of deep submicron devices in 14, 10 nm and future technologies, this design scheme becomes an attractive choice.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsReferences
Inventor: S.V. Shinde, Patent application filed, PCT/US2011/059229
S.V. Shinde, PVT insensitive reference current generation, in Proceedings of the International MultiConference of Engineers and Computer Scientists 2014, IMECS 2014, 12–14 Mar 2014, Hong Kong. Lecture Notes in Engineering and Computer Science, pp. 777–784
M. Morris Mano, Digital Design (Prentice Hall, New Jersey, 2002)
B. Razavi, Design of Analog CMOS Integrated Circuits (McGraw-Hill, New York, 2001)
P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design (Holt, Reinhart, and Winston, Inc., New York, 1987)
K.S.D. Oh, X.C.C. Yuan, High speed signaling: Jitter modeling, analysis, and budgeting. Prentice Hall modern semiconductor design series (2012)
Acknowledgment
The author wishes to thank Intel Microelectronics, HIP USB2 circuit team, Malaysia for providing necessary access to tools and Intel 22 nm process technology. Author also would like to thank IMC WPRD ETS DSI IPR PHY group, Germany for their encouragement and support on this work.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2015 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Shinde, S.V. (2015). EOS Protection for USB2 Transceiver. In: Yang, GC., Ao, SI., Huang, X., Castillo, O. (eds) Transactions on Engineering Technologies. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9588-3_23
Download citation
DOI: https://doi.org/10.1007/978-94-017-9588-3_23
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-017-9587-6
Online ISBN: 978-94-017-9588-3
eBook Packages: EngineeringEngineering (R0)