Implementation of the PSCE Circuit on Transistor Level

Abstract

It is always good practice to verify the findings of a theoretical discussion by means of practical measurement results. Hence, the Pulsed Resonant Charge Extractor (PSCE) circuit derived in the previous chapter has been implemented on transistor level in a $0.35~\mu \mathrm{m}$ technology. In the past years, this technology has well established in the field of energy harvesting, and the fabricated chips have shown a good performance. For the circuit design process, the electrical equivalent circuits of the piezoelectric harvester as derived before haven been used. One of the main goals was to reduce the average power consumption within the circuits into a regime where it can be neglected compared to the power converted by the mechanical energy harvester. One general strategy to achieve this goal is to aggressively scale down power consumption in the blocks which have to be active all the time, accepting slow operation. In constrast, higher power consumption can be allowed for blocks which have to react faster, but can be deactivated most of the time. In the following, the operation principle of the circuit blocks is explained individually in detail. Wherever possible, the blocks are grouped by their functionality, and the explanations refer to their functionality at top level. After all the blocks have been discussed, the top level implementation shows how all these blocks are combined to a top-level design. At the end of the chapter, photographs of the fabricated chip are shown.