Abstract
In this chapter, the theoretical background of the proposed Pulsed Synchronous Charge Extractor (PSCE) circuit is discussed. The principle way of power extraction used in the PSCE is based on the Synchronous Electric Charge Extraction (SECE technique, which has the potential to increase the power harvested from piezoelectric devices significantly compared to the well-known diode rectifier. However, one important point has been (deliberately) left out in the corresponding theoretical discussion: the influence of parasitic resistances on the harvested power. Since the main property of the SECE technique is to transfer the energy in a very short time slot compared to the excitation period, the current flowing during this short time can easily get as high as several ten milliamperes for transferred power in the order of few milliwatts. Subsequently, parasitic series resistances in the current path can produce significant power losses which reduce the harvested power. The techniques presented in the following have the goal to diminish these undesired power losses. Besides numerical analysis, a linear approximation is discussed, allowing to make a statement about the superiority of these techniques for any circuit parameter set.
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Hehn, T., Manoli, Y. (2015). Theory of the Proposed PSCE Circuit. In: CMOS Circuits for Piezoelectric Energy Harvesters. Springer Series in Advanced Microelectronics, vol 38. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9288-2_4
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DOI: https://doi.org/10.1007/978-94-017-9288-2_4
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