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Hardware Accelerator for Feature Point Detection and Matching

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Algorithm & SoC Design for Automotive Vision Systems

Abstract

Recently, many vehicle manufacturers have adopted a vision processing based driver assistance system (DAS) for safety. Since vehicles cannot allow any crash or collision even when running very fast, all vision algorithms should be operated in real-time without any error. Since many algorithms such as object recognition/tracking, image matching, and simultaneous localization and mapping (SLAM) are based on the interest point detection and matching algorithm, interest point detection and matching algorithms should be accelerated to provide result data for overall vision system in real-time. However, they are one of the most compute-intensive operations in DAS and even the state-of-the-art hardwired accelerators hardly achieve 60 frames per second (fps) only in VGA resolution (640 × 480). They suffer from tremendous hardware overhead because they are implemented based on heterogeneous many-core system. To overcome these limitations, we aims to implement hardware which achieve more than 90 frames per second in full HD resolution (1080p) only with 30 % of logic gates compared to the state-of-the-art object recognition processors. In this chapter, we introduces three techniques to design this hardware : (1) Joint algorithm-architecture optimizations for exploiting bit-level parallelism, (2) A low-power unified hardware platform for interest point detection and matching, and (3) scalable hardware architecture.

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Notes

  1. 1.

    http://www.robots.ox.ac.uk/~vgg/research/affine.

  2. 2.

    http://www-igm.univ-mlv.fr/~lecroq/string/.

References

  1. G. Klein, D. Murray, Simulating low-cost cameras for augmented reality composing. IEEE Trans. Visual. Comput. Graphics 16(3), 369–380 (2010)

    Article  Google Scholar 

  2. M. Ebrahimi et al., Adaptive sampling for feature detection, tracking, and recognition on mobile platforms. IEEE Trans. Circuits Syst. Video Technol. 21(10), 1467–1475 (2011)

    Article  Google Scholar 

  3. S. Kyo et al., in A 100GOPS in-vehicle vision processor based on a ring connected 128 4-way VLIW processing elements, Proc. IEEE Symp. VLSI Circuits(VLSIC ’08), 28–29 June 2008

    Google Scholar 

  4. D. Geronimo et al., Survey of pedestrian detection for advanced driver assistance systems. IEEE Trans. Pattern Anal. Mach. Intel. 32(7), 1239–1258 (2010)

    Google Scholar 

  5. D. Lowe, Distinctive image features from scale-invariant keypoints. ACM Int. J. Comput. Vision 60(2), 91–110 (2004)

    Article  Google Scholar 

  6. J.-Y. Kim et al., A 201.4GOPS 496 mW real-time multi-object recognition processor with bio-inspired neural perception engine. ISSCC Dig. Tech. Papers, 150–151 Feb 2009

    Google Scholar 

  7. S. Lee et al., A 345 mW heterogeneous many-core processor with an intelligent inference engine for robust object recognition. ISSCC Dig. Tech. Papers, 332–333 Feb 2010

    Google Scholar 

  8. E. Rosten et al., FASTER and better: a machine learning approach to corner detection. IEEE Trans. Pattern Anal. Mach. Intell. 32(1), 105–119 (2010)

    Article  Google Scholar 

  9. M. Calonder et al., BRIEF: binary robust independent elementary features. In Computer Vision–European Conference on Computer Vision (ECCV) 2010 (pp. 778–792). Springer, Berlin Heidelberg (2010)

    Google Scholar 

  10. J.-S. Park, H.-E. Kim, L.-S. Kim. A 182 mW 94.3 f/s in Full HD Pattern-Matching Based Image Recognition Accelerator for an Embedded Vision System in 0.13-um CMOS Technology. IEEE Trans. Circ. Sys. Video Tech. 23(5), 832–845 (2013)

    Google Scholar 

  11. H. Bay et al., Speeded up robust features (SURF). Comput. Vis. Image Underst. 110(3), 346–359 (2008)

    Article  Google Scholar 

  12. E. Mair et al., Adaptive and generic corner detection based on the accelerated segment test. Lect. Notes Comput. Sci. 6312, 183–196 (2010)

    Article  Google Scholar 

  13. Marek Kraft et al., System on Chip coprocessors for high speed image feature detection and matching, advanced concepts for intelligent vision systems. Lect. Notes Comput. Sci. 6915(2011), 599–610 (2011)

    Article  Google Scholar 

  14. K. Mikolajczyk et al., A performance evaluation of local descriptors. IEEE Trans. Pattern Anal. Mach. Intell. 27(10), 1615–1630 (2005)

    Article  Google Scholar 

  15. S. Winder et al., Picking the best daisy. in IEEE Conference on Computer Vision and Pattern Recognition, pp. 178–185 (2009)

    Google Scholar 

  16. A. Torralba, Small codes and large image databases for recognition, in IEEE Conference on Computer Vision and Pattern Recognition, pp. 1–8 (2008)

    Google Scholar 

  17. M. Ozuysal et al., Fast keypoint recognition using random ferms. IEEE Trans. Pattern Anal. Mach. Intell. 32, 448–461 (2010)

    Article  Google Scholar 

  18. V. Chandrasekhar et al., Compressed histogram of gradients: a low bitrate descriptor. Int. J. Comput. Vision 94(5), (2011)

    Google Scholar 

  19. B. Girod et al., Mobile visual search. IEEE Signal Process. Mag. 28(4), (2011)

    Google Scholar 

  20. E. Rublee et al., ORB : an efficient alternative to SIFT or SURF. IEEE Int. Conf. Comput. Vision (ICCV), 2564–2571 (2011)

    Google Scholar 

  21. Y. Moko et al., Implementation and evaluation of FAST corner detection on the massively parallel embedded processor MX-G. IEEE computer society conference on computer vision and pattern recognition workshops (CVPRW), 157–162 (2011)

    Google Scholar 

  22. J. Clemons et al., EFFEX: an embedded processor for computer vision based feature extraction. Design automation conference (DAC), 1020–1025, (2011)

    Google Scholar 

  23. J. Svab et al., FPGA-based speeded up robust features. IEEE international conference on technologies for practical robot applications, 35–41 (2009)

    Google Scholar 

  24. K. Dohi et al., Pattern compression of FAST corner detection for efficient hardware implementation. Int. Conf. Field Programmable Logic Appl. (FPL) 5(7), 478–481 (2011)

    Google Scholar 

  25. R.N. Horspool, Practical fast searching in strings. Softw. Pract. Experience 10(6), 501–506 (1980)

    Article  Google Scholar 

  26. R. S. Boyer, J. S. Moore, A fast string searching algorithm. Commun. ACM 20(10), (1977)

    Google Scholar 

  27. R. Baeza-Yates et al., A new approach to text searching. Commun. ACM 35(10), 74–82 (1992)

    Article  Google Scholar 

  28. M. Crochemore et al., Deux méthodes pour accélérer l’algorithme de Boyer-Moore. Théorie des Automates et Applications, Actes des 2e Journées Franco-Belges, 45–63 (1991)

    Google Scholar 

  29. R.M. Karp et al., Efficient randomized pattern-matching algorithms. IBM J. Res. Dev. 31(2), 249–260 (1987)

    Article  MATH  MathSciNet  Google Scholar 

  30. R. Baeza-Yates et al., Average running time of the BMH heuristic. Theo. comput. Sci. 92, 19–31 (1992)

    Article  MATH  MathSciNet  Google Scholar 

  31. E. Sall, M. Vesterbacka, Comparison of two thermometer-to-binary decoders for high-performance flash ADCs. NORCHIP conference, 253–256 (2005)

    Google Scholar 

  32. E. Rosten et al., Fusing points and lines for high performance tracking. IEEE Int. Conf. Comput. Vision 2, 1508–1515 (2005)

    Google Scholar 

  33. D. Nister, H. Stewenius, Scalable recognition with a vocabulary tree. IEEE Comput. Soc. Conf. Comput. Vis. Pattern Recogn. 2, 2161–2168 (2006)

    Google Scholar 

  34. H. Kim et al., A 1 mJ/Frame unified media application processor with dynamic analog-digital mode reconfiguration for embedded 3D-Media contents processing. IEEE J. Sold-State Circuits 48(8), (2013)

    Google Scholar 

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Authors and Affiliations

  1. School of EE, KAIST, Daejeon, South Korea

    Jun-Seok Park & Lee-Sup Kim

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  1. Jun-Seok Park
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  2. Lee-Sup Kim
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Correspondence to Jun-Seok Park .

Editor information

Editors and Affiliations

  1. Yonsei University, Seoul, Korea, Republic of (South Korea)

    Jaeseok Kim

  2. Hanyang University, Ansan, Korea, Republic of (South Korea)

    Hyunchul Shin

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© 2014 Springer Science+Business Media Dordrecht

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Park, JS., Kim, LS. (2014). Hardware Accelerator for Feature Point Detection and Matching. In: Kim, J., Shin, H. (eds) Algorithm & SoC Design for Automotive Vision Systems. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-9075-8_8

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  • DOI: https://doi.org/10.1007/978-94-017-9075-8_8

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  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-017-9074-1

  • Online ISBN: 978-94-017-9075-8

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