Abstract
This paper presents implementation of high-performance subtractive clustering on a single instruction multiple data (SIMD) many-core processor. Since there is no general consensus that which grain size of the many-core processor provides the maximum performance, this paper explores the effects of varying the number of processing elements (PEs) and different amount of memories by introducing image data-per-processing element (IDPE) variation as a design variable, which is the amount of image data directly mapped to each PE. In this study, five PE configurations (IDPEs = 16, 64, 256, 1,024, and 4,096) are used for evaluating the system performance in terms of execution time and system utilization. In addition, this paper compares the proposed approach with a CPU-based implementation to show the potential for the improved performance of the proposed approach. Experimental results show that the proposed approach achieves 16.73× speedup at PEs = 4,096 over the CPU-based implementation.
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Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. NRF-2013R1A2A2A05004566).
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© 2014 Springer Science+Business Media Dordrecht
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Seo, J., Kang, M., Kim, CH., Kim, JM. (2014). High-Performance Cluster Estimation Using Many-Core Models. In: Park, J., Zomaya, A., Jeong, HY., Obaidat, M. (eds) Frontier and Innovation in Future Computing and Communications. Lecture Notes in Electrical Engineering, vol 301. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-8798-7_24
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DOI: https://doi.org/10.1007/978-94-017-8798-7_24
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