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Line Edge Roughness (LER)

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Variation-Aware Advanced CMOS Devices and SRAM

Part of the book series: Springer Series in Advanced Microelectronics ((MICROELECTR.,volume 56))

Abstract

As the physical dimensions of metal oxide semiconductor field effect transistors (MOSFETs), such as physical channel length and channel width, continue to shrink at the pace described in Moore’s Law, photo-lithography technology has developed to meet the demand of printing aggressively scaled feature sizes.

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References

  1. Hashimoto K, Uesawa F, Takahata K, Kikuchi K, Kanai H, Shimizu H, Shiobara E, Takeuchi K, Endo A, Harakawa H, Miniotogi S (2003) ArF lithography technologies for 65 nm-node CMOS (CMOSS) with 30 nm logic gate and high density embedded memories. In: Symposium on VLSI Technology Digest, pp 45–46

    Google Scholar 

  2. Lin BJ (1987) The future of subhalf-micrometer optical lithography. Microcircuit Eng 6(1):31–51

    Google Scholar 

  3. Narasimha S, Onishi K, Nayfeh HM, Waite A, Weybright M, Johnson J, Fonseca C, Corliss D, Robinson C, Crouse M, Yang D, Wu C-HJ, Gabor A, Adam T, Ahsan I, Belyansky M, Black L, Butt S, Cheng J, Chou A, Costrini G, Dimitrakopoulos C, Domenicucci A, Fisher P, Frye A, Gates S, Greco S, Grunow S, Hargrove M, Holt J, Jeng S-J, Kelling M, Kim B, Landers W, Larosa G, Lea D, Lee MH, Liu X, Lustig N, McKnight A, Nicholson L, Nielsen D, Nummy K, Ontalus V, Ouyang C, Ouyang X, Prindle C, Pal R, Rausch W, Restaino D, Sheraw C, Sim J, Simon A, Standaert T, Sung CY, Tabakman K, Tian C, Van Den Nieuwenhuizen R, Van Meer H, Vayshenker A, Wehella-Gamage D, Werking J, Wong RC, Yu J, Wu S, Augur R, Brown D, Chen X, Edelstein D, Grill A, Khare M, Li Y, Luning S, Norum J, Sankaran S, Schepis D, Wachnik R, Wise R, Wann C, Ivers T, Agnello P (2006) High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography. In: Proceedings of IEEE IEDM, pp 1–4

    Google Scholar 

  4. Chen H-Y, Chang C-Y, Huang C-C, Chung T-X, Liu S-D, Hwang J-R, Liu Y-H, Chou Y-J, Wu H-J, Shu K-C, Huang C-K, You J-W, Shin J-J, Chen C-K, Lin C-H, Hsu J-W, Perng B-C, Tsai P-Y, Chen C-C, Shieh J-H, Tao H-J, Chen S-C, Gau T-S, Yang F-L (2005) Novel 20 nm hybrid SOI/Bulk CMOS technology with 0.183 μm2 6T-SRAM cell by immersion lithography. In Symposium on VLSI Technology Digest, pp 16–17

    Google Scholar 

  5. Chandhok M, Datta S, Lionberger D, Vesecky S (2007) Impact of line width roughness on Intel’s 65 nm process devices. In: Proceedings of SPIE, p 65191A

    Google Scholar 

  6. Shin C, Damrongplasit N, Sun X, Liu T-JK (2011) Performance and yield benefits of quasi-planar bulk CMOS technology for 6-T SRAM at the 22-nm node. IEEE Trans Electron Devices 58(7):1846–1854

    Article  ADS  Google Scholar 

  7. Shin C, Tsai CH, Wu MH, Chang CF, Liu YR, Kao CY, Lin GS, Chiu KL, Fu C-S, Tsai C, Liang CW, Nikolić B, Liu T-JK (2011) Quasi-planar bulk CMOS technology for improved SRAM scalability. Solid-State Electron 65–66:184–190

    Google Scholar 

  8. Shin C, Cho MH, Tsukamoto Y, Nguyen B-Y, Mazuré C, Nikolić B, Liu T-JK (2010) Performance and area scaling benefits of FD-SOI technology for 6-T SRAM cells at the 22-nm node. IEEE Trans Electron Devices 57(6):1301–1309

    Article  ADS  Google Scholar 

  9. Shin C, Park IJ (2013) Impact of using double-patterning versus single patterning on threshold voltage (VTH) variation in quasi-planar tri-gate bulk MOSFETs. IEEE Electron Device Lett 34(5):578–580

    Article  ADS  Google Scholar 

  10. Wang X, Brown AR, Cheng B, Asenov A (2011) Statistical variability and reliability in nanoscale FinFETs. In: Proceedings of IEEE IEDM, pp 5.4.1–5.4.4

    Google Scholar 

  11. Wei Y, Brainard RL (2009) Advanced processes for 193-nm immersion lithography. SPIE, Bellingham

    Book  Google Scholar 

  12. Pawloski AR, Acheta A, Bell S, La Fontaine B, Wallow T, Levinson HJ (2006) The transfer of photoresist LER through etch. In: Proceedings of SPIE, p 615318

    Google Scholar 

  13. Tsubaki H, Yamanaka T, Nishiyama F, Shitabatake K (2007) A study on the material design for the reduction of LWR. In: Proceedings of SPIE, p 651918

    Google Scholar 

  14. Tagawa S, Nagahara S, Iwamoto T, Wakita M, Kozawa T, Yamamoto Y, Werst D, Trifunac AD (2000) Radiation and photochemistry of onium salt acid generators in chemically amplified resists. In: Proceedings of SPIE, p 204

    Google Scholar 

  15. Wang X-B, Ferris K, Wang L-S (2000) Photodetachment of gaseous multiply charged anions, copper phthalocyanine tetrasulfonate tetraanion: tuning molecular electronic energy levels by charging and negative electron binding. J Phys Chem A 104(1):25–33

    Article  Google Scholar 

  16. Stewart MD, Tran HV, Schmid GM, Stachowiak TB, Becker DJ, Willson CG (2002) Acid catalyst mobility in resist resins. J Vac Sci Technol, B 20(6):2946–2952

    Article  Google Scholar 

  17. Hinsberg WD, Houle FA, Sanchez MI, Hoffnagle JA, Wallraff GM, Medeiros DR, Gallatin GM, Cobb JL (2003) Extendibility of chemically amplified resists: another brick wall? In: Proceedings of SPIE, p 1

    Google Scholar 

  18. Nam H, Lee GS, Lee H, Park IJ, Shin C (2014) Analysis of random variations and variation-robust advanced device structures. J Semicond Technol Sci 14(1)

    Google Scholar 

  19. Prabhu VM, Vogt BD, Kang S, Rao A, Lin EK, Satij SK, Turnquest K (2007) Direct measurement of the in situ developed latent image: the residual swelling fraction. In: Proceedings of SPIE, p 651910

    Google Scholar 

  20. Zhao Y (2001) Characterization of amorphous and crystalline rough surface: principles and applications. Academic Press, San Diego

    Google Scholar 

  21. Constantoudis V, Patsis GP, Tserepi A, Gogolides E (2003) Quantification of line-edge roughness of photoresists. II. Scaling and fractal analysis and the best roughness descriptors. J Vac Sci Technol B 21:1019–2003

    Article  Google Scholar 

  22. Patsis GP, Constantoudis V, Tserepi A, Gogolides E, Grozev G, Hoffmann T (2002) Roughness analysis of lithographically produced nanosturctures: off-line measurement and scaling analysis. Microelectron Eng 67–68:319–325

    Google Scholar 

  23. Constantoudis V, Patsis GP, Gogolides E (2003) Photoresist line-edge roughness analysis using scaling concepts. In: Proceedings of SPIE, p 901

    Google Scholar 

  24. Yamaguchi A, Tsuchiya R, Fukuda H, Komuro O, Kawada H, Iizumi T (2003) Characterization of line-edge roughness in resist patterns and estimations of its effect on device performance. In: Proceedings of SPIE, p 689

    Google Scholar 

  25. Bunday BD, Bishop M, Villarubia JS, Vladar AE (2003) CD-SEM measurement line-edge roughness test patterns for 193-nm lithography. In Proceedings of SPIE, p 674

    Google Scholar 

  26. Constantoudis V, Patsis GP, Leunissen LHA, Gogolides E (2004) Line edge roughness and critical dimension variation: fractal characterization and comparison using model functions. J Vac Sci Technol B 22(4):1974–1981

    Article  Google Scholar 

  27. Naulleau PP, Cain JP (2007) Experimental and model-based study of the robustness of line-edge roughness metric extraction in the presence of noise. J Vac Sci Technol B 25(5):1647–1657

    Article  Google Scholar 

  28. Barabasi A-L, Stanley HE (1995) Fractal concepts in surface growth. Cambridge University Press, Cambridge

    Book  MATH  Google Scholar 

  29. Zhao BY, Wang G-C, Lu T-M (2001) Characterization of amorphous and crystalline rough surface: principles and applications experimental methods in the physical sciences academic, New York

    Google Scholar 

  30. Bunday BD, Bishop M, McCormack D, Villarrubia JS, Vladar AE, Dixson R, Vorburger T, Orji NG, Allgair JA (2004) Determination of optimal parameters for CD-SEM measurement of line edge roughness. In: Proceedings of SPIE, p 515

    Google Scholar 

  31. Constantoudis V, Gogolides E, Roberts J, Stowers J (2005) Characterization and modeling of line width roughness (LWR). In: Proceedings of SPIE, p 1227

    Google Scholar 

  32. Patel K, Liu T-JK, Spanos CJ (2009) Gate line edge roughness model for estimation of FinFET performance variability. IEEE Trans Electron Devices 56(12):3055–3063

    Article  ADS  Google Scholar 

  33. Palasantzas G (1993) Roughness spectrum and surface width of self-affine fractal surfaces via the K-correlation model. Phys Rev B Condens Matter 48(19):14472–14478

    Google Scholar 

  34. Mahorowala P, Babich1 K, Lin Q, Medeiros DR, Petrillo K, Simons J, Angelopoulos M, Sooriyakumaran R, Hofer D, Reynolds GW, Taylor JW (2000) Transfer etching of bilayer resists in oxygen-based plasmas. J Vac Sci Technol A 18(4):1411–1419

    Google Scholar 

  35. Mahorowala AP, Goldfarb DL, Temple K, Petrillo KE, Pfeiffer D, Babich K, Angelopoulos M, Gallatin GM, Rasgon S, Sawin HH, Allen SD, Lang RN, Lawson MC, Kwong RW, Chen K-J, Li W, Varanasi PR, Sanchez MI, Ito H, Wallraff GM, Allen RD (2003) Impact of thin resist processes on post-etch LER. In: Proceedings of SPIE, p 213

    Google Scholar 

  36. Montgomery PK, Peters R, Garza C Sr, Cobb J, Darlington B, Parker C, Filipiak S, Babbitt D (2005) Reduction of line edge roughness and post resist trim pattern collapse for sub 60 nm gate patterns using gas-phase resist fluorination. In: Proceedings of SPIE, p 1024

    Google Scholar 

  37. Namatsu H, Nagase M, Yamaguchi T, Yamazaki K, Kurihara K (1998) Influence of edge roughness in resist patterns on etched patterns. J Vac Sci Technol B 16(6):3315–3321

    Article  Google Scholar 

  38. Ren F, Pearton SJ, Lothian JR, Abernathy CR, Hobson WS (1992) Reduction of sidewall roughness during dry etching of SiO2. J Vac Sci Technol B 10(6):2407–2411

    Article  Google Scholar 

  39. Ren F, Pearton SJ, Shul RJ, Han J (1998) Improved sidewall morphology on dry-etched SiO2 masked GaN features. J Electron Mater 27(4):175–178

    Article  ADS  Google Scholar 

  40. Wallow T, Acheta A, Ma Y, Pawloski A, Bell S, Ward B, Tabery C, Fontaine BL, Kim R-H, McGowan S, Levinson HJ (2007) Line-edge roughness in 193-nm resists: lithographic aspects and etch transfer. In: Proceedings of SPIE, p 651919

    Google Scholar 

  41. Goldfarb DL, Mahorowala AP, Gallatin GM, Petrillo KE, Temple K, Angelopoulos M, Rasgon S, Sawin HH, Allen SD, Lawson MC, Kwong RW (2004) Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes. J Vac Sci Technol B 22(2):647–653

    Article  Google Scholar 

  42. Steenwinckel DV, Lammers JH, Leunisse LHA, Kwinten JAJM (2005) Lithographic importance of acid diffusion in chemically amplified resists. In: Proceedings o SPIE, p 269

    Google Scholar 

  43. Hand A (2007) Applied’s litho scheme: patterning vs. printing. Semiconductor International, April 2007

    Google Scholar 

  44. Mukai H, Shiobara E, Takahashi S, Hashimoto K (2007) A study of CD budget in spacer patterning technology. In: Proceedings of SPIE, p 692406

    Google Scholar 

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Seoul, Seoul, South Korea

    Changhwan Shin

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  1. Changhwan Shin
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Correspondence to Changhwan Shin .

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Shin, C. (2016). Line Edge Roughness (LER). In: Variation-Aware Advanced CMOS Devices and SRAM. Springer Series in Advanced Microelectronics, vol 56. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7597-7_2

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