Abstract
This chapter introduces the design of three-dimensional (3D) NAND flash memory with the implications from the system side. For conventional two-dimensional (2D) scaling, it is facing various limitations such as lithography cost and cell-to-cell coupling interference. To sustain the trend of bit-cost reduction beyond 10 nm technology node, 3D NAND flash memory is considered as the next generation technique. Further, emerging memories called storage-class memories (SCMs) such as resistive RAM (ReRAM), phase change RAM (PRAM) and magnetoresistive RAM (MRAM) will revolutionize the storage system design. By introducing SCM into the solid-state drive (SSD), hybrid SCM/3D-NAND flash SSD and all SCM SSD achieve much higher write performance than all 3D-NAND flash SSD due to SCM’s fast speed. In addition, the performance of the SSD is workload dependent. Thus, it is meaningful to obtain the design guidelines of 3D NAND flash for both all 3D-NAND flash SSD and hybrid SCM/3D-NAND flash SSD with representative real-world workloads.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
K. Takeuchi, Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30 nm low-power high-speed solid-state drives (SSD). IEEE J. Solid-State Circ. 44(4), 1227–1234 (2009)
K. Takeuchi et al., A 56 nm CMOS 99 mm2 8 Gb multi-level NAND flash memory with 10-MB/s program throughput. IEEE J. Solid-State Circ. 42(1), 219–232 (2007)
C. Sun et al., SEA-SSD: a storage engine assisted SSD with application-coupled simulation platform. IEEE Trans. Circ. Syst. I 62(1), 120–129 (2015)
A.M. Caulfield et al., Moneta: a high-performance storage array architecture for next-generation, non-volatile memories, in Proceedings of the Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (2010), pp. 385–395
A.M. Caulfield et al., Providing safe, user space access to fast, solid state disks, in Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) (2012), pp. 387–400
A. Trivedi et al., Unified high-performance I/O: one stack to rule them all, in Proceedings of the USENIX Workshop on Hot Topics in Operating Systems (HotOS) (2013)
S. Peter et al., Towards high-performance application-level storage management, in Proceedings of the Workshop on Hot Topics in Storage and File System (HotStorage) (2014)
Synopsys Platform Architect, http://www.synopsys.com/Systems/ArchitectureDesign/Pages/PlatformArchitect.aspx
C. Sun et al., LBA scrambler: a NAND flash aware data management scheme for high-performance solid-state drives. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. (2015 in press)
C. Sun et al., Cost, capacity and performance analyses for hybrid SCM/NAND flash SSD. IEEE Trans. Circ. Syst. I 61(8), 2360–2369 (2014)
H. Fujii et al., x11 performance increase, x6.9 endurance enhancement, 93 % energy reduction of 3D TSV-integrated hybrid ReRAM/MLC NAND SSDs by data fragmentation suppression, in IEEE Symposium on VLSI Circuits (2012), pp. 134–135
C. Sun et al., A high performance and energy-efficient cold data eviction algorithm for 3D-TSV hybrid ReRAM/MLC NAND SSD. IEEE Trans. Circ. Syst. I 61(2), 382–392 (2014)
C. Sun et al., SCM capacity and NAND over-provisioning requirements for SCM/NAND flash hybrid enterprise SSD, in Proceedings on International Memory Workshop (IMW) (2013), pp. 64–67
J. Jang et al., Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory, in IEEE Symposium on VLSI Technology (2009), pp. 192–193
R. Katsumata et al., Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices, in IEEE Symposium on VLSI Technology (2009), pp. 136–137
J. Kim et al., Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and cost-effective NAND flash memory devices and SSD (Solid State Drive), in IEEE Symposium on VLSI Technology (2009), pp. 186–187
S.J. Whang et al., Novel 3-dimentional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1 Tb file storage application, in IEEE International Electron Devices Meeting (IEDM) (2010), pp. 668–671
K. Miyaji et al., Control gate length, spacing, channel hole diameter, and stacked layer number design for bit-cost scalable-type three-dimensional stackable NAND flash memory. Jpn. J. Appl. Phys. 53, 024201 (2014)
C. Lee et al., A 32 Gb MLC NAND-flash memory with Vth-endurance-enhancing schemes in 32 nm CMOS, in Proceedings IEEE International Solid-State Circuits Conference (ISSCC), Feb 2010, pp. 446–447
K. Fukuda et al., A 151 mm2 64 Gb MLC flash memory in 24 nm cmos technology, in Proceedings on IEEE International Solid-State Circuits Conference (ISSCC), Feb 2011, pp. 198–199
S. Choi et al., A 93.4 mm2 64 Gb MLC NAND-flash memory with 16 nm cmos technology, in Proceedings on IEEE International Solid-State Circuits Conference (ISSCC), Feb 2014, pp. 328–329
M. Sako et al., A low-power 64 Gb MLC NAND-flash memory in 15 nm cmos technology, in Proceedings on IEEE International Solid-State Circuits Conference (ISSCC), Feb 2014, pp. 128–129
C. Sun et al., A workload-aware-design of 3D-NAND flash memory for enterprise SSDs, in International Symposium on Quality Electronic Design (ISQED), March 2014, pp. 554–561
Micron Technology Inc., MT29512G08CUCAB data sheet, Nov 2009, http://micron.com
K. Higuchi et al., Evaluation of voltage vs. pulse width modulation and feedback during set/reset verify-programming to achieve 10 million cycles for 50 nm HfO2 ReRAM. Solid-State Electron. 91, 67–73 (2014)
T. Onagi et al., Design guidelines of storage class memory based solid-state drives to balance performance, power, endurance and cost. Jpn. J. Appl. Phys. (JJAP) (2015 in press)
R. Fackenthal et al., A 16 Gb ReRAM with 200 MB/s write and 1 GB/s read in 27 nm technology, in Proceedings on IEEE International Solid-State Circuits Conference (ISSCC), Feb 2014, pp. 338–339
M. Helm et al., A 128 Gb MLC NAND-flash device using 16 nm planar cell, in Proceedings on IEEE International Solid-State Circuits Conference (ISSCC), Feb 2014, pp. 326–327
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2016 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Sun, C., Takeuchi, K. (2016). System-Level Considerations on Design of 3D NAND Flash Memories. In: Micheloni, R. (eds) 3D Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-94-017-7512-0_12
Download citation
DOI: https://doi.org/10.1007/978-94-017-7512-0_12
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-017-7510-6
Online ISBN: 978-94-017-7512-0
eBook Packages: Computer ScienceComputer Science (R0)