VLSI Interconnection by Bumpless TAB

Abstract

TAB has always been associated with bumps and gang bonding. This situation has been an advantage for people requiring high throughput in production as demonstrated in the Japanese electronic industry; it has been a difficulty for other people willing to start prototyping with TAB or needing only small quantities of components.

Among the drawbacks, the non recurring costs associated with a TAB configuration are not acceptable for small runs; the same way, delays in obtaining the tape, bumping, and the associated tooling are often considered as too long.

An other difficulty comes from the increasing size of VLSI chips which are no longer easily compatible with the gang bonding operation.

A new ILB technique called single point bonding, has been applied in the industry starting five years ago; it is consist in replacing the collective bionding by a point by point bonding operation peformed on a modified wire bonder. This has first allowed to handle large size chips which were not mountable by gang bonding; but the most interesting of it is that it has allowed to give up the need for wafer bumping of aluminum pads.

Several companies have developed this process and some of them have it in production.

This paper describes the development which has been made at BULL, through European Community sponsored packaging programs and which is being now supported by the DGA/DRET French adinistration in association with a large French company for military MCM applications.

Examples of memories and of high performance ASIC’s are described, as well as the associated reliability evaluations.

Through these developments, bumpless ILB has shown to be a reliable alternative for bumped TAB devices; in conjunction with an effort to speed up design time and tape procurements. It appears to be an attractive solution for newcomers in TAB applications.