Abstract
This article examines the origin and nature of mechanical stress and possible failure of interconnects in microelectronics, involving both the global interconnect and the intermetal dielectric.
Results from thin film processing illustrate the importance of thin film microstructure (topography) and its relation to that of the underlayer in determining the interconnect properties.
Materials characterization, stress measurements and modeling of stress effects in interconnect underlayer structures, have been accomplished with an Optical Surface Scattering (OSS) technique, the application of a custom windows-based software package and the use of holographic interferometry. Results from each category are presented.
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© 1998 Springer Science+Business Media Dordrecht
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Gielisse, P.J., Tu, M., White, D.Y., Famu-Fsu, Y.X. (1998). Mechanical Stress in Microelectronic Interconnects. In: Harman, G., Mach, P. (eds) Microelectronic Interconnections and Assembly. NATO ASI Series, vol 54. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-5135-1_13
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DOI: https://doi.org/10.1007/978-94-011-5135-1_13
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-010-6159-9
Online ISBN: 978-94-011-5135-1
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