Abstract
ASICs will continue to grow increasingly complex. Errors of specification, design and implementation are unavoidable. Consequently, designers need validation methods and tools to ensure a perfect design before the production is started. Errors caught after fabrication incur not only added production costs, but also delay the product, which is an increasingly serious detriment in today’s fast-paced international markets. “First-time-right silicon” is, therefore, one of the most important goals of chip-design projects.
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Rosenstiel, W. (1999). Rapid Prototyping, Emulation and Hardware-Software Co-Debugging. In: Jerraya, A.A., Mermet, J. (eds) System-Level Synthesis. NATO Science Series, vol 357. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-4698-2_7
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DOI: https://doi.org/10.1007/978-94-011-4698-2_7
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