Abstract
SOI technology with trench isolation has increased packing density of bipolar integrated circuits and improved their performance through a significant reduction in parasitic capacitance. A further improvement in performance could be obtained if the collector series resistance was reduced. This paper examines the technology for the incorporation of a metal silicide layer between the silicon layer and the buried oxide. These silicon on silicide on insulator (S2OI) layers are characterised using MOS and p-n junction test structures and shown to be of device quality. Examples are presented from the literature of possible applications for S2OI substrates. A post bond polish stop process suitable for producing nanometre thick S2OI layers for research device structures is outlined. Finally, a new process for producing complementary bipolar circuits using S2OI substrates is proposed.
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Gamble, H.S. (2000). Polish Stop Technology for Silicon on Silicide on Insulator Structures. In: Hemment, P.L.F., Lysenko, V.S., Nazarov, A.N. (eds) Perspectives, Science and Technologies for Novel Silicon on Insulator Devices. NATO Science Series, vol 73. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-4261-8_2
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DOI: https://doi.org/10.1007/978-94-011-4261-8_2
Publisher Name: Springer, Dordrecht
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