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Electrical Instabilities in Silicon-on-Insulator Structures and Devices During Voltage and Temperature Stressing

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Perspectives, Science and Technologies for Novel Silicon on Insulator Devices

Part of the book series: NATO Science Series ((ASHT,volume 73))

Abstract

Electrical instabilities in silicon-on-insulator (SOI) materials and devices during voltage and thermal stressing are fundamentally due to the movement and trapping of charge in the buried oxide (BOX), this being electrically the least robust part of the SOI structures. These processes will be controllerd both by the intrinsic structure and the impurity composition of the BOX and by the properties of the BOX/semiconductor interfaces and charge trapping into the BOX after the charge injection from outer layers.

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Authors and Affiliations

  1. Institute of Semiconductor Physics, NAS of Ukraine, Prospect Nauki 45, 252028, Kyiv, Ukraine

    A. N. Nazarov, I. P. Barchuk & V. I. Kilchytska

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  1. A. N. Nazarov
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  2. I. P. Barchuk
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  3. V. I. Kilchytska
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Editors and Affiliations

  1. University of Surrey, Guildford, Surrey, UK

    Peter L. F. Hemment

  2. Institute of Semiconductor Physics, Kyiv, Ukraine

    V. S. Lysenko  & A. N. Nazarov  & 

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Nazarov, A.N., Barchuk, I.P., Kilchytska, V.I. (2000). Electrical Instabilities in Silicon-on-Insulator Structures and Devices During Voltage and Temperature Stressing. In: Hemment, P.L.F., Lysenko, V.S., Nazarov, A.N. (eds) Perspectives, Science and Technologies for Novel Silicon on Insulator Devices. NATO Science Series, vol 73. Springer, Dordrecht. https://doi.org/10.1007/978-94-011-4261-8_15

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  • DOI: https://doi.org/10.1007/978-94-011-4261-8_15

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