Novel TESC Bipolar Transistor Approach for a Thin-Film Silicon-On-Insulator Substrate

Abstract

Silicon-on-Insulator (SoI) technology offers an advanced electronic material structure suitable for realisation of a high performance bipolar transistor (BT). In this work, we demonstrate a route to a high performance thin-film BT on SoI fabricated using Sol-CMOS process for future thin-film SoI-BiCMOS circuits. The proposed novel approach to a thin-film BT has a device structure with a highly efficient Top poly-silicon Emitter and a low resistance N+ Side-Collector (TESC). An npn TESC-BT was fabricated on an 85nm thinned silicon overlayer of SIMOX material. Good common-emitter output characteristics of the npn TESC-BT were obtained, demonstrating the viable underlying concept of a TESC approach for a bipolar transistor fabricated on thin-film SoI substrate. The evaluated lateral pinched base resistance of 4kΩ for a 20µm long TESC device is reflected in the collector current role-off at a very high current density (6000Acm⁻²). A reduction in the base Gummel number, as a consequence of back-gate biasing the TESC device dramatically enhances the current gain and induces drift current favourable for achieving higher ft. Under such baising conditions or with a suitable doping profile, a 2-dimensional bipolar operation can occur. The TESC device offers the potential for realising vertical bipolar operation in a very thin-film silicon overlayer by inverting the back-interface, which acts as an extended side collector, thus improving the collecting efficiency. The TESC approach to bipolar transistor in a thin-film SoI was found to be a versatile device which can sustain, both the lateral and vertical bipolar operation.