Abstract
If we are looking for ways to implement high-performance systems, there are several directions we can head. One direction is to use high-speed technologies, such as bipolar or GaAs, which allow us to gain performance without modification to the methods or algorithms. If, in contrast, we wish to exploit one of the low-cost VLSI technologies, particularly CMOS, we can gain much more impressive advantages in performance by exploiting concurrency in addition to speed. This is because, while the scaling of these technologies does naturally result in higher speed (roughly proportional to the reciprocal of the scaling factor), it has a much more dramatic effect on the available complexity (which increases roughly as the square of the speed)[1]. Two other characteristics which lead to high performance implementations should also be kept in mind. First, it is desirable to use structures with localized communications, since communications is expensive in speed, power, and die area. Second, it is desirable to achieve localized timing, meaning that whenever signals must propagate a long distance there is available a suitable delay time[2].
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References
J.W. Goodman, F.J. Leonberger, S-Y Kung, and R.A. Athale, “Optical Interconnections for VLSI Systems,” IEEE Proceedings 72(7) p. 850 (July 1984).
S. Y. Kung, “On Supercomputing with Systolic/Wavefront Array Processors,” Proceedings of the IEEE 72(7)(July 1984).
H. T. Kung, “Why Systolic Architectures,” IEEE Computer 15(1)(Jan. 1982).
M. Honig and D.G. Messerschmitt, Adaptive Filters: Structures, Algorithms, and Applications, Kluwer Academic Press, Hingham, Mass. (1985).
H. T. Kung and Charles E. Leiserson, “Algorithms for VLSI Processor Arrays,” in Mead and Conway, Introduction to VLSI Systems, Wesley Publishing Co., Reading, MA (October, 1980).
Hassan M. Ahmed, Jean-Marc Delosme, and Martin Morf, “Highly Concurrent Computing Structures for Matrix Arithmetic and Signal Processing,” IEEE Computer 15(1)(Jan. 1982).
Sailesh K. Rao and Thomas Kailath, VLSI and The Digital Filtering Problem, Information Systems Laboratory, Stanford University,, Stanford (1984). Internal Memorandum
Hui-Hung Lu, Edward A. Lee, and David G. Messerschmitt, “Fast Recursive Filtering with Multiple Slow Processing Elements,” IEEE Transactions on Circuits and Systems. (November, 1985).
C.W. Wu, P.R. Cappello, and M. Saboff. “An FIR Filter Tissue.” Proc. 19th Asilomar Conf. on Circuits, Systems, and Computers, (Nov. 1985).
J. Robert Jump and Sudhir R. Ahuja. “Effective Pipelining of Digital Systems,” IEEE Trans, on Computers C-27(9)(Sept., 1978).
Cappello, Peter R. and Steiglitz, Kenneth, “A VLSI Layout for a Pipelined Data Multiplier,” ACM Transactions on Computer Systems 1 (2) p. 157 (May 1983).
Luk, W. K., “A Regular Layout for Parallel Multiplier of $0(Log sup 2 N)$ Time,” pp. 317 in VLSI Systems and Computations, ed. Guy Steele. Computer Science Press, Rockville, Md. (1981).
Reusens, Peter, Ku, Walter H., and Mao, Yu-hai, “Fixed Point High Speed Parallel Multipliers in VLSI,” pp. 301 in VLSI Systems and Computations, ed. Guy Steele. Computer Science Press, Rockville, Md. (1981).
Brent, R.P. and Kung, H.T., “A Regular Layout for Parallel Adders,” Technical Report, Dept of Computer Science, Carnegie-Mellon University CMU.CS.79.131 (June 1979).
Parhi, Keshab Kumar and Messerschmitt, David G., “A Bit Level Pipelined Systolic Recursive Filter Architecture,” Proceedings of the International Conference on Computer Design,, (1986).
K. Parhi and D.G. Messerschmitt, “Efficient Implementation of Recursive Filters Pipelined at Bit Level,” IEEE Trans, on Acoustics, Speech, and Signal Processing, ((submitted)).
Markku Renfors and Yrjo Neuvo, “The Maximum Sampling Rate of Digital Filters Under Hardware Speed Constraints.” IEEE Trans, on Circuits and Systems CAS-28(3)(March 1981).
A. Fettweis, “Realizability of Digital Filter Networks,” Arch. Elek. Ubertrangung 30 pp. 90–96 (Feb. 1976).
Charles E. Leiserson and Flavio M. Rose, “Optimizing Synchronous Circuitry by Retiming,” Third Caltech Conference on VLSI, (March. 1983).
Hui-Hung Lu, High Speed Recursive Filtering, University of California, Berkeley (1983). PhD Thesis
David G. Messerschmitt, VLSI Implemented Signal Processing Algorithms, NATO Advanced Study Institute, Bonas, France (July 1983). Conference
B. Gold and K. L. Jordan, “A Note on Digital Filter Synthesis.” Proceedings of the IEEE 65 pp. 1717–1718 (Oct., 1968).
H. B. Voelcker and E. E. Hartquist, “Digital Filtering Via Block Recursion,” IEEE Trans. Audio and Electroacoustics AU-18 pp. 169–176 (June 1970).
Charles S. Burrus, “Block Implementation of Digital Filters,” IEEE Trans, on Circuit Theory CT-18 pp. 697–701 (Nov. 1971).
Casper W. Barnes and S. Shinnaka, “Block Shift Invariance and Block Implementation of Discrete-Time Filters.” IEEE Transactions on Circuits and Systems CAS-27 pp. 667–672 (Aug., 1980).
Sanjit K. Mitra and R. Gnanasekaran, “Block Implementations of Recursive Digital Filters — New Structures and Properties,” IEEE Trans, on Circuits and Systems CAS-25 pp. 200–207 (April, 1978).
Jan Zeman and Allen G. Lindgren, “Fast Digital Filters with Low Round-oif Noise.” IEEE Trans, on Circuits and Systems CAS-28 pp. 716–723 (July 1981).
D. A. Schwartz and T. P. Barnwell, III, “Increasing the Parallelism of Filters Through Transformation to Block State Variable Form,” Proceedings of ICASSP ’84, San Diego, (1984).
Chrysostomos L. Nikias, “Fast Block Data Processing via a New IIR Digital Filter Structure.” IEEE Transactions on ASSP 32(4)(August, 1984).
Teresa H.-Y. Meng and D.G. Messerschmitt, “Implementations of Arbitrarily Fast Adaptive Lattice Filters With Multiple Slow Processing Elements,” Proc. IEEE ICASSP, (April 1986).
Teresa H.-Y. Meng and D.G. Messerschmitt. “Arbitrarily High Sampling Rate Adaptive Filters,” IEEE Trans, on Acoustics, Speech, and Signal Processing, ((to appear)).
K. Parhi and D.G. Messerschmitt. “Bit Level Pipelined Adaptive Filters,” IEEE Trans. on Acoustics, Speech, and Signal Processing, ((submitted)).
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© 1988 Kluwer Academic Publishers
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Messerschmitt, D.G. (1988). Breaking the Recursive Bottleneck. In: Skwirzynski, J.K. (eds) Performance Limits in Communication Theory and Practice. NATO ASI Series, vol 142. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-2794-0_1
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DOI: https://doi.org/10.1007/978-94-009-2794-0_1
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