Abstract
A methodology is presented which aims to improve CMOS ASIC reliability. It differs from conventional reliability assessment techniques as it is based on an understanding of CMOS failure effects at the circuit-level. The first step of this approach requires a yield and failure analysis programme of CMOS ASICs to be established. The programme results are then used to simulate the effects of CMOS failures at the circuit-level and evaluate test patterns. The final step uses this knowledge to provide guidelines for test pattern generation and fault coverage comparisons.
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© 1990 Kluwer Academic Publishers
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Davies, M.S., O’Connor, P.D.T. (1990). Reliability Assessment of Cmos Asic Designs. In: Christou, A., Unger, B.A. (eds) Semiconductor Device Reliability. NATO ASI Series, vol 175. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-2482-6_8
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DOI: https://doi.org/10.1007/978-94-009-2482-6_8
Publisher Name: Springer, Dordrecht
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