Monte Carlo Simulation for Reliability Physics Modeling and Prediction of Scaled (100 nm) Silicon Mosfet Devices

Abstract

Since the early 1970’s, silicon integrated circuit technology has been propelled by continual and successful efforts to reduce the active channel length of MOSFET devices [1–3]. This exercise in scaling provides the framework that has produced increases in the density of devices on a chip, increases in device frequency response and operating speed, and increases in the precision required to achieve more complex systems with greater functionality and performance. Today, devices with channel lengths well below 100 nm have been produced in many research laboratories, and the downward scaling trends of the past twenty years are expected to persist at the same pace until at least the 40 nm generation in manufacturing [1], or about the year 2015. This level of technology is expected to correspond to 128 GBit DRAMs and 28 Ggate microprocessors with five times the clock frequency and 1/9 the power consumption of today’s devices, all operating at a power supply voltage of around 0.5 V.