Abstract
Technology dependent trends are projected for high performance processors. There are opposite demands placed on the system’s area stemming from a need to reduce the proportion of interconnection capacitance and to send signals across the processor. Delays resulting from wiring capacitance decrease if processor area increases, while signal travel considerations favor reducing area. This trade-off for bipolar processors is governed by power density, while for CMOS the processor size primarily is determined by wiring considerations. Judicious planning of interconnections to avoid a so called “RC crises” is necessary to achieve the potential inherent in a technology. The performance limits of bipolar and room temperature CMOS uni-processors are very similar. The highest performance existing technology is liquid nitrogen temperature CMOS. It is not obvious how alternate technologies will fit into the picture of future general-purpose high-end systems.
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© 1996 IBM
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Sai-Halasz, G.A. (1996). Processor Performance Scaling. In: Luryi, S., Xu, J., Zaslavsky, A. (eds) Future Trends in Microelectronics. NATO ASI Series, vol 323. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-1746-0_11
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DOI: https://doi.org/10.1007/978-94-009-1746-0_11
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