Abstract
The analysis of today’s neural paradigmas brings to light a set of elementary compute-intensive algorithmic strings which are shared by all neural models and, thus, make sense to be implemented in hardware. 2D arrays composed of a systolic neural signal processor module that integrates these elementary strings as hard-wired functional blocks present a favourable solution to the architectural problem of mapping neural parallelity and adaptivity into silicon. The proposed neurocomputer concept is sizeable to the applicational domain in terms of processing power, memory and flexibility, and is designed for throughput rates which enable the user to access real-world applications in reasonable time. Throughput rates at the chip site of the order of 5·102 MC/sec (1 Connection= 16 bit) are to be expected with 0.8µm CMOS technology. By systolic extension to the board level 105 MC/sec should be attainable.
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© 1990 Springer Science+Business Media Dordrecht
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Ramacher, U., Wesseling, M., Goser, K. (1990). Systolic Synthesis of Neural Networks. In: International Neural Network Conference. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-0643-3_6
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DOI: https://doi.org/10.1007/978-94-009-0643-3_6
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