A Reconfigurable Architecture for a VLSI Implementation of Artificial Neural Networks

Abstract

In this paper, a VLSI design of a Basic Neural Unit (BNU) for artificial neural networks (ANNs) is proposed. The BNU is used as a basic processing element in constructing an ANN. An important issue to address in the design of BNU is to reduce the interconnection complexity of ANNs. When the size of an ANN grows, the number of synaptic weights connected to each neuron increases rapidly. From the hardware implementation point of view, an expandable and reconfigurable architecture design for ANNs is in demand. A new approach has been used in designing a BNU. This BNU design is the foundation of a reconfigurable architecture for constructing an ANN with a very strong expandability.

Weight-centered approach, in contrast with the traditional neuron-centered view, is the key point to this new architecture design. The weight-centered idea intends to transfer the processing load from a neuron to a number of synaptic weight branches, thus decentralizing the computation task. Adding more neurodes, when enlarging the size of an ANN, is accomplished by merely appending more weighted branches. In. VLSI implementation, this is achieved by plugging in one or more BNU chips. The weight-centered design approach enhances the reconfigurability and expandability of an ANN. This design has since been fabricated on a silicon chip by the IBM corporation.