Abstract
A neural network emulator is described in this paper. The device can implement neural networks of various architectures, provided that the inputs and outputs of neurons are binary.
The device is fully digital. It is mainly composed of 128 serial adders, and can be viewed as a 128 processor specialized SIMD machine. It can emulate neural layers of any size, only depending on the amount of RAM attached (a fully connected Boltzmann machine with 351 neurons has been implemented).
As an example of application, graph bisection using a Boltzmann machine is discussed on the basis of results obtained using the prototype.
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References
Patrice Bertin, Didier Roncin and Jean Vuillemin, Introduction to Programmable Active Memories, in Systolic Array Processors, Prentice Hall, 1989; also available as Research Report Nr 2, Digital Equipment Corporation Paris Research Laboratory, 1989.
Emile Aarts and Jan Korst, Simulated Annealing and Boltzmann Machines,Wiley, 1989.
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© 1990 Springer Science+Business Media Dordrecht
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Skubiszewski, M. (1990). A Hardware Emulator for Binary Neural Networks. In: International Neural Network Conference. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-0643-3_2
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DOI: https://doi.org/10.1007/978-94-009-0643-3_2
Publisher Name: Springer, Dordrecht
Print ISBN: 978-0-7923-0831-7
Online ISBN: 978-94-009-0643-3
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