Abstract
Neural network simulations are often limited because of the time required for both the learning and the evaluation phase of the simulation. Our parallel digital LNcuro circuit drastically reduces these times by updating synaptic coefficients related to one neuron in parallel. Contributions of ‘input’ neurons to one output neuron are also computed in parallel.
LNeuro-chips can easily be associated using Transputer microprocessors as controllers. Boards communicate through the reconfigurable links provided by a SuperNode architecture. This allows to simulate large size-networks or structured network architectures like Multi-Layer Perceptrons.
We report demonstrations of a parallel system built with several LNcuro-chips, which include a local learning rule (on a ‘real-time’ application), and the famous Backpropagation algorithm.
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References
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© 1990 Springer Science+Business Media Dordrecht
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Theeten, J.B., Duranton, M., Mauduit, N., Sirat, J.A. (1990). The LNeuro-Chip: A Digital VLSI with on-Chip Learning Mechanism. In: International Neural Network Conference. Springer, Dordrecht. https://doi.org/10.1007/978-94-009-0643-3_11
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DOI: https://doi.org/10.1007/978-94-009-0643-3_11
Publisher Name: Springer, Dordrecht
Print ISBN: 978-0-7923-0831-7
Online ISBN: 978-94-009-0643-3
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