Circuit Modelling of Control Flow

Abstract

In the preceding chapter, we discussed techniques for constructing a self-timed circuit given by the model of a finite state machine. These are certainly not the only possible techniques: for example, we can also specify the behaviour of a synthesized circuit, by means of flow charts, cyclo-diagrams, timing diagrams etc. In Chapter 2, we described a group of behavioural models among which the asynchronous process (AP) was fundamental, and the other models were generated by AP as particular interpretations of the latter. In this chapter, we shall discuss methods for constructing self-timed circuits using the terminology presented in Chapter 2.

I realize very clearly what time is until I am asked to explain what it is. I always lose the meaning when I attempt the explanation.

Saint Augustine

In the original: “Quid ergo est tempus? Si nemo ex me querat scio; si quaerenti explicare velim, nescio”.