As mentioned in previous chapter, there have been great efforts to study the trap or midgap states in real devices and semiconducting thin-films so far. Photoluminescence (PL) is a direct method to observe deep-level defects in semiconductors but can not be used on a working device with interfaces [1, 2]. Deep-level transient spectroscopy (DLTS) and gate-bias stress techniques may be used with working TFT devices to characterize the interface trap states, utilizing thermal and electrical energies, respectively [2, 3, 4, 5, 6, 7]. However, DLTS has its own limit due to poor resolution on unpractical devices while deep-level in DLTS is actually not too deep because of the limit of temperature elevation. Gate bias stress technique is only an industrial test which can not resolve the density-of-states in trap energy level. In this chapter we thus display the instrumentation of photo-excited charge-collection spectroscopy (PECCS) on a working TFT device. .
Deep-level defects PECCS TFT Monochromator Photon-probe Trap DOS
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