Abstract
In the Pre-Error AVS scheme the timing information is provided by in-situ delay monitors (Pre-Error flip-flops), that detect late but still non-erroneous data transitions in critical paths. Late data transitions are defined by the pre-error detection window, i.e. a defined time interval T pre before the triggering edge of the clock.
The timing of digital circuits is influenced by PVTA variations and so is the frequency of pre-errors. The pre-error rate, indicating the timing slack, is thus used to adapt the supply voltage on-the-fly/on-line, i.e. during normal circuit operation. During each N clock cycles, forming an observation interval, the number of pre-errors n pre is counted and it is decided whether to change the voltage subsequently. For a pre-error count n pre under a lower threshold n limit↓, the voltage is decreased by ΔV DD . If the count is above the upper limit n limit↑, the voltage will be increased by ΔV DD . For counts inside the limits the voltage is maintained.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsNotes
- 1.
The two most common hardware description languages are VHDL and Verilog.
References
M. Wirnshofer, L. Heiss, G. Georgakos, D. Schmitt-Landsiedel, A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring, in Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (2011), pp. 261–266
M. Wirnshofer, L. Heiss, G. Georgakos, D. Schmitt-Landsiedel, An energy-efficient supply voltage scheme using in-situ pre-error detection for on-the-fly voltage adaptation to PVT variations, in Proceedings of the 13th International Symposium on Integrated Circuits (ISIC) (2011), pp. 94–97
M. Wirnshofer, L. Heiss, A.N. Kakade, N. Pour Aryan, G. Georgakos, D. Schmitt-Landsiedel, Adaptive voltage scaling by in-situ delay monitoring for an image processing circuit, in Proceedings of the 15th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) (2012), pp. 205–208
G.A. Rincon-Mora, P.E. Allen, A low-voltage, low quiescent current, low drop-out regulator. IEEE J. Solid-State Circuits 33(1), 36–44 (1998)
M. Lüders, B. Eversmann, J. Gerber, K. Huber, R. Kuhn, D. Schmitt-Landsiedel, R. Brederlow, A fully-integrated system power aware LDO for energy harvesting applications, in Proceedings of the Symposium on VLSI Circuits (VLSI) (2011), pp. 244–245
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Wirnshofer, M. (2013). Adaptive Voltage Scaling by In-situ Delay Monitoring. In: Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Series in Advanced Microelectronics, vol 41. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6196-4_4
Download citation
DOI: https://doi.org/10.1007/978-94-007-6196-4_4
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-6195-7
Online ISBN: 978-94-007-6196-4
eBook Packages: EngineeringEngineering (R0)