Abstract
As discussed in the previous chapter, process, voltage and temperature variations as well as aging significantly affect the timing of digital circuits. To cope with these uncertainties, worst-case guard-banding is still the most common design approach. As the worst-case is very rare however, in most cases power or performance is wasted by this approach.
By scaling the operating voltage, energy efficiency can be increased. Tuning the supply voltage dependent on PVTA variations is referred to as adaptive voltage scaling (AVS). The term AVS is often interchanged with dynamic voltage scaling (DVS), but note that DVS considers only varying workloads and does not adapt to PVTA variations at all. To clarify the difference between both techniques, they are explained in the following two sections.
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Notes
- 1.
Arbitrarily changing the duty cycle is of course only possible, if the negative clock edge is not used to trigger any logic events.
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Wirnshofer, M. (2013). Related Work. In: Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits. Springer Series in Advanced Microelectronics, vol 41. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-6196-4_3
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