Abstract
In order to ensure the reliability of embedded systems, test of the embedded system memory is particularly important. Among the different types of algorithms proposed for testing memories, March test is the most popular one. Due to directly accessing memory, during the memory test, cache must be turned off, which greatly reduces the speed of memory access. In accordance with the characteristics of MPC8572 development platform and the memory fault models, we propose a method to speed up March test which takes advantage of cache to store data from memory for the CPU. However, turning on cache can mask many memory fault models. CPU can’t directly access memory, which causes memory test results inaccurate. In this paper, we focus on the impact of cache on memory test and analyze how cache can mask the memory fault models. Then, bases on this analysis, we propose a method to speed up March test. For different March operations, configuring the cache speeds up the memory test.
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© 2012 Springer Science+Business Media Dordrecht
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Hu, D., Wu, J., Zhu, X., Wang, Y., Jiang, B. (2012). The Impact of Cache on Memory Test. In: Park, J., Jeong, YS., Park, S., Chen, HC. (eds) Embedded and Multimedia Computing Technology and Service. Lecture Notes in Electrical Engineering, vol 181. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-5076-0_15
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DOI: https://doi.org/10.1007/978-94-007-5076-0_15
Publisher Name: Springer, Dordrecht
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