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Reconfigurable Memristor Fabrics for Heterogeneous Computing

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Advances in Neuromorphic Memristor Science and Applications

Part of the book series: Springer Series in Cognitive and Neural Systems ((SSCNS,volume 4))

Abstract

Device scaling and performance limits in complementary metal-oxide-semiconductor (CMOS) technology are leading to a rapid proliferation of novel computing paradigms for information processing. To this end, CMOS/memristor hybrid technology, where memristive devices are integrated in 3D, is extremely promising. These technologies are emerging under the joint efforts of industry and academe, with innovations in fabrication processes, materials, devices, and circuits. A prime advantage of such computing technology is its ability to offer tera-bit densities with ultra low power and long data retention times. These unique characteristics motivate the development of computational fabrics that can dynamically transform over time to perform heterogeneous computing based on system requirements, with the technological objective of superseding classical CMOS architectures. This book chapter discusses the different models of memristors which can be used for implementing memristors as memory, sensing, logic and nueromorphic units.

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References

  1. Chua L (1971, September) Memristor-the missing circuit element. IEEE Trans Circuit Theory 18(5):507–519

    Article  Google Scholar 

  2. Jo SH (2010) Nanoscale memristive devices for memory and logic applications. Ph.D. dissertation, University of Michigan

    Google Scholar 

  3. Xia Q, Robinett W, Cumbie MW, Banerjee N, Cardinali TJ, Yang JJ, Wu W, Li X, Tong WM, Strukov DB, Snider GS, Medeiros-Ribeiro G, Williams RS (2009) Memristor/CMOS hybrid integrated circuits for reconfigurable logic. Nano Lett 9(10):3640–3645 [Online]. http://pubs.acs.org/doi/abs/10.1021/nl901874j

    Article  PubMed  CAS  Google Scholar 

  4. Cannon E, KleinOsowski A, Kanj R, Reinhardt D, Joshi R (2008, March) The impact of aging effects and manufacturing variation on SRAM soft-error rate. IEEE Trans Dev Mater Reliab 8(1):145–152

    Article  Google Scholar 

  5. Bernstein K, Frank DJ, Gattiker AE, Haensch W, Ji BL, Nassif SR, Nowak EJ, Pearson DJ, Rohrer NJ (2006, July) High-performance CMOS variability in the 65-nm regime and beyond. IBM J Res Dev 50(4.5):433–449

    Article  Google Scholar 

  6. Pang L-T, Qian K, Spanos C, Nikolic B (2009, August) Measurement and analysis of variability in 45 nm strained-si CMOS technology. IEEE J Solid-State Circ 44(8):2233–2243

    Article  Google Scholar 

  7. Chua L, Kang SM (1976, February) Memristive devices and systems. Proc IEEE 64(2):209–223

    Article  Google Scholar 

  8. Argall F (1968) Switching phenomena in titanium oxide thin films. Solid-State Electron 11:535–541

    Article  CAS  Google Scholar 

  9. Blanc J, Staebler DL (1971, November) Electrocoloration in SrTiO3: vacancy drift and oxidation–reduction of transition metals. Phys Rev B 4(10):3548

    Article  Google Scholar 

  10. Strukov DB, Snider GS, Stewart DR, Williams RS (2008, May) The missing memristor found. Nature 453(7191):80–83 [Online]. http://dx.doi.org/10.1038/nature06932

    Article  PubMed  CAS  Google Scholar 

  11. Dong Y, Yu G, McAlpine MC, Lu W, Lieber CM (2008) Si/a-Si core/shell nanowires as nonvolatile crossbar switches. Nano Lett 8(2):386–391 (pMID: 18220442) [Online]. http://pubs.acs.org/doi/abs/10.1021/nl073224p

    Article  PubMed  CAS  Google Scholar 

  12. Jo SH, Lu W (2008) CMOS compatible nanoscale nonvolatile resistance switching memory. Nano Lett 8(2):392–397 (pMID: 18217785) [Online]. http://pubs.acs.org/doi/abs/10.1021/nl073225h

    Article  PubMed  CAS  Google Scholar 

  13. Jo SH, Kim K-H, Wei L (2009) Programmable resistance switching in nanoscale two-terminal devices. Nano Lett 9(1):496–500

    Article  PubMed  CAS  Google Scholar 

  14. Jo SH, Kim K-H, Lu W (2009) High-density crossbar arrays based on a Si memristive system. Nano Lett 9(2):870–874 [Online]. http://pubs.acs.org/doi/abs/10.1021/nl8037689

    Article  PubMed  CAS  Google Scholar 

  15. Yang YC, Pan F, Liu Q, Liu M, Zeng F (2009) Fully room-temperature-fabricated nonvolatile resistive memory for ultrafast and high-density memory application. Nano Lett 9(4):1636–1643

    Article  PubMed  CAS  Google Scholar 

  16. Yang JJ, Pickett MD, Li X, Ohlberg DAA, Stewart DR, Williams RS (2008) Memristive switching mechanism for metal/oxide/metal nanodevices. Nat Nanotechnol 3(7):429–433

    Article  PubMed  CAS  Google Scholar 

  17. Pickett MD, Strukov DB, Borghetti JL, Yang JJ, Snider GS, Stewart DR, Williams RS (2009, October) Switching dynamics in titanium dioxide memristive devices. J Appl Phys 106(7):074 508–074 508-6

    Article  Google Scholar 

  18. Pershin YV, Di Ventra M (2008, September) Spin memristive systems: spin memory effects in semiconductor spintronics. Phys Rev B 78(11):113309

    Article  Google Scholar 

  19. Deng W-Q, Muller RP, Goddard WA (2004) Mechanism of the Stoddart-Heath bistable rotaxane molecular switch. J Am Chem Soc 126(42):13 562–13 563 (pMID: 15493882) [Online]. http://pubs.acs.org/doi/abs/10.1021/ja036498x

    Article  Google Scholar 

  20. Gergel-Hackett N, Hamadani B, Dunlap B, Suehle J, Richter C, Hacker C, Gundlach D (2009, July) A flexible solution-processed memristor. Electron Dev Lett IEEE 30(7):706–708

    Article  CAS  Google Scholar 

  21. Prodromakis T, Michelakis K, Toumazou C (2010) Fabrication and electrical characteristics of memristors with TiO2/TIO2 + x active layers. In: Circuits and systems (ISCAS), Proceedings of 2010 IEEE international symposium on, 30 2010-June 2 2010, pp 1520–1522

    Google Scholar 

  22. Jo SH, Kim K-H, Lu W (2009) High-density crossbar arrays based on a Si memristive system. Nano Lett 9(2):870–874 [Online]. http://pubs.acs.org/doi/abs/10.1021/nl8037689

    Article  PubMed  CAS  Google Scholar 

  23. Manem H, Rose GS (2011) A read-monitored write circuit for 1T1M multilevel memristor memories. In: Circuits and systems (ISCAS), 2011 IEEE international symposium on, May 2011, pp 2938–2941

    Google Scholar 

  24. Chua L, Kang SM (1976, February) Memristive devices and systems. Proc IEEE 642:209–223

    Article  Google Scholar 

  25. Wang FY (2008, August) Memristor for introductory physics. eprint arXiv:0808.0286v1 [physics.class-ph]

    Google Scholar 

  26. Joglekar YN, Wolf SJ (2009, July)The elusive memristor: properties of basic electrical circuits. Eur J Phys 30:661–675

    Article  CAS  Google Scholar 

  27. Strukov DB, Borghetti JL, Williams RS (2009) Coupled ionic and electronic transport model of thin-film semiconductor memristive behavior. Small 5(9):1058–1063

    Article  PubMed  CAS  Google Scholar 

  28. Glicksman ME (2000) Diffusion in solids: field theory, solid-state principles, and applications. Wiley, New York

    Google Scholar 

  29. Weinert U, Mason EA (1980) Generalized Nernst--Einstein relations for nonlinear transport coefficients. Phys Rev A 21(2):681–690

    Article  CAS  Google Scholar 

  30. Strukov D, Williams R (2009) Exponential ionic drift: fast switching and low volatility of thin-film memristors. Appl Phys A: Mater Sci Process 94:515–519. doi:10.1007/s00339-008-4975-3 [Online]. http://dx.doi.org/10.1007/s00339-008-4975-3

    Article  CAS  Google Scholar 

  31. Benderli S, Wey T (2009, March 26) On spice macromodelling of TiO2 memristors. Electron Lett 45(7):377–379

    Article  CAS  Google Scholar 

  32. Zdenek B, Dalibor B, Viera B (2010) Spice model of memristor with nonlinear dopant drift. Radioeng J 30(4):210–214

    Google Scholar 

  33. Shin S, Kim K, Kang S-M (2010, April) Compact models for memristors based on charge--flux constitutive relationships. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(4):590–598

    Article  Google Scholar 

  34. Rak A, Cserey G (2010, April) Macromodeling of the memristor in spice. IEEE Trans Comput-Aided Des Integr Circuits Syst 29(4):632–636

    Article  Google Scholar 

  35. Pino R, Bohl J, McDonald N, Wysocki B, Rozwood P, Campbell K, Oblea A, Timilsina A (2010) Compact method for modeling and simulation of memristor devices: ion conductor chalcogenide-based memristor devices. Proceedings of the IEEE/ACM international symposium on nanoscale architectures (NANOARCH), pp 1–4, June 2010

    Google Scholar 

  36. Itoh M, Chua L (2008) Memristor oscillators. Int J Bifurc Chaos 18(11):3183–3206

    Article  Google Scholar 

  37. Linn E, Rosezin R, Kugeler C, Waser R (2010, April) Complementary resistive switches for passive nanocrossbar memories. Nat Mater 9(5):403–406

    Article  PubMed  CAS  Google Scholar 

  38. Manem H, Rose GS, He X, Wang W (2010) Design considerations for variation tolerant multilevel CMOS/nano memristor memory. In: Proceedings of the 20th symposium on Great lakes symposium on VLSI, ser. GLSVLSI ’10. New York, NY, USA: ACM, 2010, pp 287–292 [Online]. http://doi.acm.org/10.1145/1785481.1785548

    Google Scholar 

  39. Vontobel PO, Robinett W, Kuekes PJ, Stewart DR, Straznicky J, Williams RS (2009) Writing to and reading from a nano-scale crossbar memory based on memristors. Nanotechnology 20(42):425 204–425 223

    Article  Google Scholar 

  40. Qureshi MS, Pickett M, Miao F, Strachan JP (2011) CMOS interface circuits for reading and writing memristor crossbar array. In: Circuits and systems (ISCAS), 2011 IEEE international symposium on, May 2011, pp 2954–2957

    Google Scholar 

  41. Chen Y-S, Liu W-H, Lee H-Y, Chen P-S, Wang S-M, Tsai C-H, Hsu Y-Y, Gu P-Y, Chen W-S, Chen F, Lien C-H, Tsai M-J (2011) Impact of compliance current overshoot on high resistance state, memory performance, and device yield of HfOx based resistive memory and its solution. In: VLSI technology, systems and applications (VLSI-TSA), 2011 international symposium on, April 2011, pp 1–2

    Google Scholar 

  42. Strukov DB, Likharev KK (2005) CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices. Nanotechnology 16:888–900

    Article  CAS  Google Scholar 

  43. Snider GS, Williams SR (2007) Nano/CMOS architectures using a field-programmable nanowire interconnect. Nanotechnology 18(3):1–10

    Article  Google Scholar 

  44. Robinett W, Snider G, Stewart D, Straznicky J, Williams R (2007, May) Demultiplexers for nanoelectronics constructed from nonlinear tunneling resistors. IEEE Trans Nanotechnol 6(3):280–290

    Article  Google Scholar 

  45. Ho Y, Huang G, Li P (2009) Nonvolatile memristor memory: device characteristics and design implications. In: Computer-aided design—digest of technical papers, 2009. ICCAD 2009. IEEE/ACM international conference on, November 2009, pp 485–490.

    Google Scholar 

  46. Niu D, Chen Y, Xie Y (2010) Low-power dual-element memristor based memory design. In: Proceedings of the 16th ACM/IEEE international symposium on low power electronics and design, ser. ISLPED ’10. New York, NY, USA: ACM, 2010, pp 25–30 [Online]. http://doi.acm.org/10.1145/1840845.1840851

    Google Scholar 

  47. Merkel CE (2011) Thermal profiling in CMOS/memristor hybrid architectures. Master’s thesis, Rochester Institute of Technology

    Google Scholar 

  48. Kim H, Sah M, Yang C, Chua L (2010) Memristor-based multilevel memory. In: Cellular nanoscale networks and their applications (CNNA), 2010 12th international workshop on, February 2010, pp 1–6

    Google Scholar 

  49. Merkel CE, Nagpal N, Mandalapu S, Kudithipudi D (2011) Reconfigurable n-level memristor memory design. In: International joint conference on neural networks, 2011

    Google Scholar 

  50. Choi J, Cher C-Y, Franke H, Hamann H, Weger A, Bose P (2007) Thermal-aware task scheduling at the system software level. In: Proceedings of the 2007 international symposium on low power electronics and design, ser. ISLPED ’07. New York, NY, USA: ACM, 2007, pp 213–218 [Online]. http://doi.acm.org/10.1145/1283780.1283826

    Google Scholar 

  51. Burd T, Pering T, Stratakos A, Brodersen R (2000) A dynamic voltage scaled microprocessor system. In: Solid-state circuits conference, 2000. Digest of technical papers. ISSCC. 2000 IEEE international, 2000, pp 294–295, 466

    Google Scholar 

  52. Merrikh-Bayat F, Shouraki SB (2011) Memristor-based circuits for performing basic arithmetic operations. Proc Comput Sci, pp 128–132

    Google Scholar 

  53. Mead C (1990, October) Neuromorphic electronic systems. Proc IEEE 78(10):1629–1636

    Article  Google Scholar 

  54. Jo SH, Chang T, Ebong I, Bhadviya BB, Mazumder P, Lu W (2010) Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett 10(4):1297–1301 (pMID: 20192230) [Online]. http://pubs.acs.org/doi/abs/10.1021/nl904092h

    Article  PubMed  CAS  Google Scholar 

  55. Rose GS, Pino R, Wu Q (2011) A low-power memristive neuromorphic circuit utilizing a global/local training mechanism. In: Neural networks (IJCNN), the 2011 international joint conference on, July 31 2011-August 5 2011, pp 2080–2086

    Google Scholar 

  56. Snider G (2008) Spike-timing-dependent learning in memristive nanodevices. In: Nanoscale architectures, 2008. NANOARCH 2008. IEEE International Symposium on, June 2008, pp 85–92

    Google Scholar 

  57. Afifi A, Ayatollahi A, Raissi F (2009) Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits. In: Circuit theory and design, 2009. ECCTD 2009. European conference on, August 2009, pp 563–566

    Google Scholar 

  58. Pershin YV, Di Ventra M (2011) Neuromorphic, digital and quantum computation with memory circuit elements. eprint arXiv:1009.6025v3 [cond-mat.mes-hall]

    Google Scholar 

  59. Choi S-J, Kim G-B, Lee K, Kim K-H, Yang W-Y, Cho S, Bae H-J, Seo D-S, Kim S-I, Lee K-J (2011) Synaptic behaviors of a single metal–oxide–metal resistive device. Appl Phys A: Mater Sci Process 102:1019–1025. doi:10.1007/s00339-011-6282-7 [Online]. http://dx.doi.org/10.1007/s00339-011-6282-7

    Article  CAS  Google Scholar 

  60. Linares-Barranco B, Serrano-Gotarredona T, Camuñas-Mesa LA, Perez-Carrasco JA, Zamarreño-Ramos C, Masquelier T (2011) On spike-timing-dependent-plasticity, memristive devices, and building a self-learning visual cortex. Front Neurosci 5:26

    PubMed  Google Scholar 

  61. Merrikh-Bayat F, Shouraki SB (2010) Bottleneck of using single memristor as a synapse and its solution. eprint arXiv:1008.3450v2 [cs.NE]

    Google Scholar 

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Correspondence to Dhireesha Kudithipudi .

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Kudithipudi, D., Merkel, C.E. (2012). Reconfigurable Memristor Fabrics for Heterogeneous Computing. In: Kozma, R., Pino, R., Pazienza, G. (eds) Advances in Neuromorphic Memristor Science and Applications. Springer Series in Cognitive and Neural Systems, vol 4. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-4491-2_7

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