Abstract
Traditionally, performance evaluation of networks-on-chip (NoC) is largely based on simulation which, besides being extremely slow, provides little insight on how different design parameters can affect the actual network performance. Therefore, it is practically impossible to use simulation for optimization purposes. This chapter presents a mathematical model for on-chip routers and utilize this new model for NoC performance analysis. The model presented in this chapter can be used not only to obtain fast and accurate performance estimates, but also to guide the NoC design process within an optimization loop. The accuracy of our approach and its practical use is illustrated through extensive simulation results.
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Notes
- 1.
Our assumptions and router model are detailed in Sect. 5.5.
- 2.
The PASTA definition implies that the distribution of packets in the system that is seen by a new (arriving) packet is the same as the long run (time asymptotic) or steady state of the packet distribution. This allows us to relate the mean waiting time a packet in the buffer with the mean number of packets in all the buffers of the router.
- 3.
Equivalently, the eigenvalues of matrices \(T\Uplambda C_{1}\) and \(T \Uplambda C_{1}\) are less than one.
- 4.
Note that, in this chapter, we use A \(\ge \) B to denote the element-wise comparison for two matrices of same dimensions.
- 5.
When \(P = 1 \), this condition reduces to \(\lambda T < 1\) known as the stability condition for a single buffer.
- 6.
Each mapping is simulated 100 times and the average latency over all runs is used for ranking to increase the confidence level of the results. Run-time comparisons against a single simulation run are presented in Sect. 5.6.5.
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Ogras, U.Y., Marculescu, R. (2013). NoC Performance Analysis. In: Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures. Lecture Notes in Electrical Engineering, vol 184. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-3958-1_5
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