Abstract
This research is to design a dynamic data packing and flushing method for buffer architecture to improve write performance of Hybrid Solid State Disk (HSDD), combined with Single Level Cell (SLC) and Multi Level Cell (MLC) flash memory, for multimedia applications. SLC has relatively excellent endurance and performance and is expensive, whereas MLC has relatively bad endurance and performance and is cheap. As short and frequent write requests (random request) are transferred in SLC and long and infrequent write requests (sequential request) are transferred in MLC, HSSD processes write requests efficiently to enhance its overall endurance. To optimize the write performance of HSSD, access pattern is analyzed to devise a decision function to determine random or sequential request, which can be one of major media accessing characteristics. Specifically data must be written in parallel for maximum sequential allocation in case of multimedia applications. But it is difficult to detect precise access pattern of requests, because several requests tend to be mixed by multi-processing. Also data tend to be written intensively in some specific logical blocks. Thus, data being written should be pushed and packed into the buffer to enhance the degree of sequential write. And the data to be flushed is selected by the condition of HSSD. The proposed buffering method shows better performance by 42% on average than basic buffering structure. Although an overhead occurred by additional structure in proposed architecture is considered.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Agrawal N, Prabhakaran V, Wobber T, Davis JD, Manasse M, Panigraphy R (2008) Design tradeoffs for SSD performance. In: Proceedings of the USENIX annual technical conference
Dumitru D (2007) Understanding flash SSD performance. http://managedflash.com/news/papers/easycoflashperformance-art.pdf
Bisson T, Brandt SA (2007) Reducing hybrid disk write latency with flash-backed I/O Requests. In: Proceedings of the 15th IEEE international symposium on modeling, analysis, and simulation of computer and telecommunication systems, MASCOTS’07
Chang L (2008) Hybrid solid-state disks: combining heterogeneous NAND flash in large SSDs. Design automation conference, pp 428–433
Park S, Park J, Kim S, Weems C (2010) A pattern adaptive NAND flash memory storage structure. IEEE transactions on computers, 06 October 2010, IEEE computer society digital library. IEEE computer society. http://doi.ieeecomputersociety.org/10.1109/TC.2010.212
Park J, Park S, Weems C, Kim S (2011) A hybrid flash translation layer for SLC-MLC flash memory based multibank solid state disk. Microprosessors Microsys 35(1):48–59
Jo H, Kang J, Park S, Kim J, Lee J (2006) Fab: flash-aware buffer management policy for portable media players. IEEE Trans Consum Electron 52(02):485–493
Micron Technology Inc. (2006) MT29F1GxxABB 1Â Gb NAND flash memory. http://download.micron.com/pdf/datasheets/flash/nand/1gb_nand_m48a.pdf
Jung S, Song Y (2009) Hierarchical use of heterogeneous flash memories for high performance and durability consumer electronics. IEEE Trans 55:1383–1391
Chung T, Park D, Park S, Lee D, Lee S, Song H (2009) A survey of flash translation layer. J Syst Archit: The EUROMICRO J 55:332–343
Kang J, Jo H, Kim J, Lee J (2006) A superblock-based flash translation layer for NAND flash memory. EMSOFT’06
Dirik C, Jacob B (2009) The performance of PC solid-state disks (SSDs) as a function of bandwidth. Concurrency, Device, Architecture, and System Organization, ISCA’09
Jacob B, Ng S, Wang D (2007) Memory systems: cache, DRAM, disk. Morgan Kaufmann, San Fransisco
Park J, Bahn HKK (2009) Buffer cache management for combined MLC and SLC flash memories using both volatile and nonvolatile RAMs. IEEE international conference on embedded and real-time computing systems and applications, pp 228–235
Kim H, Ahn S (2008) BPLRU:a buffer management scheme for improving random writes in flash storage. In: Proceedings of the 6th USENIX symposium on file and storage technologies. FAST’08 239–252
Acknowledgements
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2011-0002536).
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer Science+Business Media B.V.
About this paper
Cite this paper
Cho, IP., Ko, SH., Yang, HM., Kim, CG., Kim, SD. (2012). A Dynamic Buffer Management of Hybrid Solid State Disk for Media Applications. In: Kim, K., Ahn, S. (eds) Proceedings of the International Conference on IT Convergence and Security 2011. Lecture Notes in Electrical Engineering, vol 120. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2911-7_23
Download citation
DOI: https://doi.org/10.1007/978-94-007-2911-7_23
Published:
Publisher Name: Springer, Dordrecht
Print ISBN: 978-94-007-2910-0
Online ISBN: 978-94-007-2911-7
eBook Packages: EngineeringEngineering (R0)