Abstract
Arithmetic structures are a major building block for digital signal processing tasks. Inherent pipelining in Adiabatic Logic can be advantageously used to implement compact and energy efficient arithmetic units. Ripple-carry-adder and different parallel-prefix adders are rated with respect to energy and area consumption. Efficient arithmetic structures in Adiabatic Logic can only be implemented if a massive overhead due to synchronization signals caused by the inherent pipelining property of Adiabatic Logic is prevented. Design procedures are presented. Multi-operand adders can be either constructed by carry-save adder structures or ripple-carry adders without major synchronization effort in Adiabatic Logic. A Discrete Cosine Transformation based on a CORDIC is shown to be a diverse arithmetic structure that due to its butterfly structure is ideally suited for implementation with Adiabatic Logic. An exhaustive investigation gives energy dissipation figures and a comparison to static CMOS on arithmetic system level.
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Teichmann, P. (2012). Arithmetic Structures in Adiabatic Logic. In: Adiabatic Logic. Springer Series in Advanced Microelectronics, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2345-0_6
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DOI: https://doi.org/10.1007/978-94-007-2345-0_6
Publisher Name: Springer, Dordrecht
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