Abstract
Portable communication and infotainment devices are a major driver to explore ways to operate electronic circuits in an energy efficient manner. Besides enabling longer operating time by higher energy storage densities within batteries and more efficient display technologies, the consumption within electronic circuits has to be reduced. A brief survey shows the history of reversible computation and Adiabatic Logic and explains why Adiabatic Logic outperforms the traditional static CMOS when ultra-low energy dissipation is the main focus.
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V. Tiwari, D. Singh, S. Rajgopal, G. Mehta, R. Patel, F. Baez, Reducing power in high-performance microprocessors, in Proceedings of the 35th Annual Design Automation Conference. San Francisco, CA (ACM, New York, 1998), pp. 732–737
R.K. Krishnamurthy, A. Alvandpour, S. Mathew, M. Anders, V. De, S. Borkar, High-performance, low-power, and leakage-tolerance challenges for sub-70nm microprocessor circuits, in Proceedings of the 28th European Solid-State Circuits Conference, 2002, pp. 315–321
R.K. Krishnamurthy, S.K. Mathew, M.A. Anders, S.K. Hsu, H. Kaul, S. Borkar, High-performance and low-voltage challenges for sub-45nm microprocessor circuits, in 6th International Conference on ASIC, vol. 1, 2005, pp. 283–286
D. Pham, M. Alexander, A. Arizpe, B. Burgess, C. Dietz, L. Eisen, R. El-Kareh, J. Eno, S. Gary, G. Gerosa, B. Goins, J. Golab, R. Golla, R. Harris, B. Ho, Y.-W. Ho, K. Hoover, C. Hunter, P. Ippolito, R. Jessani, J. Kahle, K.R. Kishore, B. Kuttanna, S. Litch, S. Mallick, T. Ngo, D. Ogden, C. Olson, S.-H. Park, R. Patel, M. Pham, J. Prado, S. Reeve, R. Reininger, H. Sanchez, M. Schiffli, J. Slaton, G. Thuraisingham, K. Torku, C. Tran, N. Vanderschaaf, P. Voldstad, A 3.0 W 75SPECint92 85SPECfp92 superscalar RISC microprocessor, in IEEE International Solid-State Circuits Conference, 1994, pp. 212–213
L. Benini, P. Siegel, G. De Micheli, Saving power by synthesizing gated clocks for sequential circuits. IEEE Design & Test of Computers 11(4), 32–41 (1994)
W.P. Maly, Integrated circuit, device, system, and method of fabrication. US Patent PCT/US2007/011630, 2007
W. Maly, Y.-W. Lin, M. Marek-Sadowska, OPC-Free and Minimally Irregular IC Design Style, in Proc. 44th ACM/IEEE Design Automation Conference DAC ’07, 4–8 June 2007, pp. 954–957
W. Maly, A. Pfitzner, Complementary vertical slit field effect transistors, Technical Report No. CSSI 08-02, CSSI, Carnegie Mellon University, January 2008
E. Amirante, Adiabatic Logic in Sub-quartermicron CMOS Technologies. Selected Topics of Electronics and Micromechatronics, vol. 13 (Shaker, Aachen, 2004)
J. Fischer, Adiabatische Schaltungen und Systeme in Deep-Submicron-CMOS-Technologien. Selected Topics of Electronics and Micromechatronics, vol. 24 (Shaker, Aachen, 2006)
E. Amirante, J. Fischer, M. Lang, A. Bargagli-Stoffi, J. Berthold, C. Heer, D. Schmitt-Landsiedel, An ultra low-power adiabatic adder embedded in a standard 0.13 μm CMOS environment, in Proceedings of the 29th European Solid-State Circuits Conference, 2003, pp. 599–602
R. Landauer, Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5, 183–191 (1961)
C.H. Bennett, Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)
E. Fredkin, T. Toffoli, Conservative logic. Int. J. Theor. Phys. 21(3–4), 219–253 (1982)
J.S. Hall, An electroid switching model for reversible computer architectures, in Workshop on Physics and Computation, 1992, pp. 237–247
J.G. Koller, W.C. Athas, Adiabatic switching, low energy computing, and the physics of storing and erasing information, in Proc. Workshop on Physics and Computation, 1992, pp. 267–270
A. Kramer, J.S. Denker, B. Flower, J. Moroney, 2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits, in Proceedings of the International Symposium on Low Power Design (ACM, New York, 1995), pp. 191–196
A. Vetuli, S.D. Pascoli, L.M. Reyneri, Positive feedback in adiabatic logic. Electron. Lett. 32(20), 1867–1869 (1996)
Y. Moon, D.-K. Jeong, An efficient charge recovery logic circuit. IEEE J. Solid-State Circuits 31(4), 514–522 (1996)
V.G. Oklobdzija, D. Maksimovic, F. Lin, Pass-transistor adiabatic logic using single power-clock supply. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. 44(10), 842–846 (1997)
D. Maksimovic, V.G. Oklobdzija, B. Nikolic, K.W. Current, Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental results, in Proc. International Symposium on Low Power Electronics and Design, 1997, pp. 323–327
S. Kim, M.C. Papaefthymiou, True single-phase energy-recovering logic for low-power, high-speed VLSI, in Proc. International Symposium on Low Power Electronics and Design, 1998, pp. 167–172
C. Kim, S.-M. Yoo, S.-M.S. Kang, Low-power adiabatic computing with NMOS energy recovery logic. Electron. Lett. 36(16), 1349–1350 (2000)
H. Jianping, C. Lizhang, L. Xiao, A new type of low-power adiabatic circuit with complementary pass-transistor logic, in 5th International Conference on ASIC, vol. 2, 2003, pp. 1235–1238
V.S. Sathe, M.C. Papaefthymiou, C.H. Ziesler, A GHz-class charge recovery logic, in Proc. International Symposium on Low Power Electronics and Design, 2005, pp. 91–94
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Teichmann, P. (2012). Introduction. In: Adiabatic Logic. Springer Series in Advanced Microelectronics, vol 34. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2345-0_1
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