Abstract
With the widespread use of embedded system, efficient and low-power designs have become crucial. The increasing scale of circuits leads to many problems in traditional synchronous designs. Asynchronous circuits use handshake signals to control communications between different modules, resolving problems caused by global clock. In order to implement full-asynchronous communications between asynchronous devices, this paper studies key techniques about asynchronous bus and implements an asynchronous bus, Pipeline-based Asynchronous bus for low energy (PABLE). We propose an asynchronous pipeline structure to improve bus’s performance and research the asynchronous arbitration circuit to provide a stable and efficient asynchronous mechanism. Experimental results show that, for a single transfer, the read or write latency of PABLE would be lower than synchronous bus in the case of more than 60%. The average power consumption of PABLE decreases by 41% compared with synchronous bus.
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Acknowledgments
This work is supported by National Natural Science Foundation of China under Grant No.60873015 and Innovation Fund of Graduate School of National University of Defense Technology under Grant Nos. S100605, B100601 and CX2010B026.
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Zhang, G., Wang, Z., Lu, H., Wang, Y., Chen, F. (2011). Design of an Efficient Low-Power Asynchronous Bus for Embedded System. In: Park, J., Jin, H., Liao, X., Zheng, R. (eds) Proceedings of the International Conference on Human-centric Computing 2011 and Embedded and Multimedia Computing 2011. Lecture Notes in Electrical Engineering, vol 102. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-2105-0_39
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DOI: https://doi.org/10.1007/978-94-007-2105-0_39
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