Abstract
A 12b 2.9GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an IM3 < −60dBc beyond 1 GHz while driving a 50 Ω load with an output swing of 2.5Vppd and dissipating a power of 188 mW. The SFDR measured at 2.9 GS/s is better than 60 dB beyond 340 MHz while the SFDR measured at 1.6 GS/s is better than 60 dB beyond 440 MHz. The increase in performance at high-frequencies, compared to previously published results, is mainly obtained by adding local cascodes on top of the current-switches with “always-ON” biasing.
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Bult, K. et al. (2012). A 12b 2.9 GS/s DAC with IM3<–60 dBc Beyond 1 GHz in 65 nm CMOS. In: Steyaert, M., van Roermund, A., Baschirotto, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1926-2_6
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DOI: https://doi.org/10.1007/978-94-007-1926-2_6
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