Skip to main content
SpringerLink
Log in

Ultra High Data Rate CMOS Front Ends

  • Chapter
  • First Online:
Analog Circuit Design

  • 4386 Accesses

Abstract

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Refernces

  1. Commun. Netw. 1 (2007). pp. 50

    Google Scholar 

  2. S. Cherry, Edholm’s law of bandwidth. IEEE Spectr. 41(7), 58–60 (2004)

    Article  Google Scholar 

  3. Noise Figure Measurement Accuracy – The Y-Factor Method, Agilent Application note 57–2, http://cp.literature.agilent.com/litweb/pdf/5952-3706E.pdf

  4. J. Borremans, K. Raczkowski, P. Wambacq, A digitally controlled compact 57-to-66 GHz front-end in 45 nm digital CMOS. ISSCC 2009, San Francisco, Feb 2009

    Google Scholar 

  5. D.J. Cassan, J.R. Long, A 1 V transformer-feedback low-noise-amplifier for 5 GHz wireless LAN in 0.18 μm CMOS. IEEE J. Solid-State Circ. 38(3), 427–435 (2003)

    Article  Google Scholar 

  6. H.M. Cheema, E. Janssen, R. Mahmoudi, A. van Roermund, Monolithic transformers for high frequency bulk CMOS circuits, in IEEE Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems 2009. SiRF ′09, ed. by J. William (IEEE, San Diego, 2009), pp. 1–4

    Chapter  Google Scholar 

  7. E. Cohen, S. Ravid, D. Ritter, An ultra low power LNA with 15dB Gain and 4.4 dB NF in 90nm CMOS process for 60GHz phase array radio. IEEE RFIC Symposium of Digest, June 2008, pp. 61–64

    Google Scholar 

  8. A. Siligaris, C. Mounet, B. Reig, P. Vincent, A. Michel, CMOS SOI technology for WPAN. Application to 60 GHz LNA. IEEE ICIDT, International Conference. 2008

    Google Scholar 

  9. T. Yao, M.Q. Gordon, K.K.W. Tang, K.H.K. Yau, M.-T. Yang, P. Schvan, S.P. Voinigescu, Algorithmic design of CMOS LNAs and PAs for 60 GHz radio. IEEE J. Solid-State Circ. 42(5), 1044–1057 (2007)

    Article  Google Scholar 

  10. C. Weyers, P. Mayr, J.W. Kunze, U. Langmann, A 22.3 dB voltage gain 6.1 dB NF 60 GHz LNA in 65 nm CMOS with differential output. ISSCC Digest of Technical Papers, Feb 2008

    Google Scholar 

  11. P. Sakian, R. Mahmoudi, P. van Zeijl, M. Lont, A. van Roermund, A 60-GHz double-balanced homodyne down-converter in 65-nm CMOS Process, 2009. European Microwave Integrated Circuits Conference, Rome, Sept. 2009

    Google Scholar 

  12. C.E. Shannon, Communication in the presence of noise. Proc. IEEE 72(9), 1192–1201 (1984)

    Article  Google Scholar 

  13. D. Manstretta, M. Brandolini, F. Svelto, Second-order intermodulation mechanisms in CMOS downconverters. IEEE J. Solid State Circ. 38(3), 394–406 (2003)

    Article  Google Scholar 

  14. J. Wang, A.K.K. Wong, Effects of mismatch on CMOS double-balanced mixers: a theoretical analysis. IEEE Hong Kong Electron Devices Meeting, Hong Kong, 2001

    Google Scholar 

  15. K. Dufrene, R. Weigel, A novel IP2 calibration method for low-voltage down conversion mixers. IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, June 2006

    Google Scholar 

  16. K. Kivekas, A. Parssinen, J. Ryynanen, J. Jussila, K. Halonen, Calibration techniques of active BiCMOS mixers. IEEE J. Solid State Circ. 37(6), 766–769 (2002)

    Article  Google Scholar 

  17. M. Hotti, J. Ryynanen, K. Kievekas, K. Halonen, An IIP2 calibration technique for direct conversion receivers. IEEE International Symposium on Circuits and Systems (ISCAS), 2004

    Google Scholar 

  18. S.K. Reynolds, B.A. Floyd, U.R. Pfeiffer, T. Beukema, J. Grzyb, C. Haymes, B. Gaucher, M. Soyuer, A silicon 60 GHz receiver and transmitter chipset for broadband communications. IEEE J. Solid-State Circ. 41(12), 2820–2831 (2006)

    Article  Google Scholar 

  19. C.-H. Wang, C.-C. Chen, M.-F. Lei, et al., A 66-72 GHz divide-by-3 injection-locked frequency divider in 0.13-μm CMOS technology. IEEE Asian Solid-State Circuits Conference, Nov 2007, pp. 344–347

    Google Scholar 

  20. Yu Xiao Peng, A 3 mW 54.6 GHz divide-by-3 injection locked frequency divider with resistive harmonic enhancement. IEEE Microw. Wirel. Compon. Lett. 19(9), 575–577 (2009)

    Article  Google Scholar 

  21. H.-K. Chen, H.-J. Chen et al., A mm-wave CMOS multimode frequency divider. ISSCC Digest of Technical Papers, Feb. 2009, pp. 280–281

    Google Scholar 

  22. S.-W. Tam, H.-T. Yu, Y. Kim, E. Socher, M.C.F. Chang, T. Itoh, A dual band mm-wave CMOS oscillator with left-handed resonator. IEEE Radio Frequency Integrated Circuits Symposium, June 2009, pp. 477–480

    Google Scholar 

  23. Luo Tang-Nian, Chen Yi-Jan Emery, A 0.8-mW 55 GHz dual-injection-locked CMOS frequency divider. IEEE Trans. Microw. Theory Tech. 56(3), 620–625 (2008)

    Article  Google Scholar 

  24. H.-K. Chen, D.-C. Chang, Y.-Z. Juang, S.-S. Lu, A 30-GHz wideband low-power CMOS injection- locked frequency divider for 60 GHz wireless- LAN. IEEE Microw. Wirel. Compon. Lett. 18(2), 145–147 (2008)

    Article  Google Scholar 

  25. I. Aoki, S. Kee, D. Rutledge, A. Hajimiri, Distributed active transformer-a new power combining and impedance-transformation technique. Microw. Theory Tech., IEEE Trans. 50(1), 316–331 (2002)

    Article  Google Scholar 

  26. T. Cheung, J. Long, Y. Tretiakov, D. Harame, A 21-27 GHz selfshielded 4-way power-combining pa balun, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE, 2004

    Google Scholar 

  27. J.-W. Lai, A. Valdes-Garcia, A 1v 17.9dbm 60 GHz power amplifier in standard 65 nm CMOS, in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010. IEEE International, 2010

    Google Scholar 

  28. P. Haldi, D. Chowdhury, P. Reynaert, G. Liu, A. Niknejad, A 5.8 GHz 1v linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS. Solid-State Circ. IEEE J. 43(5), 1054–1063 (2008)

    Article  Google Scholar 

  29. U.R. Pfeiffer, D. Goren, A 23-dbm 60-GHz distributed active transformer in a silicon process technology. Microw. Theory Tech., IEEE Trans. 55(5), 857–865 (2007)

    Article  Google Scholar 

  30. Y. Pei, A 60 GHz, 12.5 GHz 1db bandwidth fully integrated power amplifier using a distributed ring transformer in CMOS 65 nm. Master thesis, Eindhoven University of Technology, Aug 2010

    Google Scholar 

  31. O, Richard et al., A 17.5-to-20.94 GHz and 35-to-41.88 GHz PLL in 65 nm CMOS for wireless HD applications. IEEE International Solid-State Circuits Conference, Feb. 2010, pp. 252–253

    Google Scholar 

  32. S. Pellerano, R. Mukhopadhyay, A. Ravi, J. Laskar, Y. Palaskas, A 39.1-to-41.6 GHz ΔΣ fractional-N frequency synthesizer in 90 nm CMOS. IEEE International Solid-State Circuits Conference, Feb. 2008, pp. 484–485

    Google Scholar 

  33. C. Changhua, D. Yanping, K.O. Kenneth, A 50 GHz phase-locked loop in 0.13-mm CMOS. IEEE J. Solid-State Circ. 42(8), 1649–1656 (2007)

    Article  Google Scholar 

  34. C. Lee, S.I. Liu, A 58-to-60.4 GHz frequency synthesizer in 90 nm CMOS. IEEE International Solid-State Circuits Conference, Feb 2007, pp. 196–197

    Google Scholar 

  35. A. Siligaris, Y. Hamada, C. Mounet, C. Raynaud, B. Martineau, N. Deparis, N. Rolland, M. Fukaishi, P. Vincent, A 60 GHz power amplifier with 14.5dBm saturation power and 25Circuits. IEEE J. Solid-State Circ. 45(7), 1286–1294 (2010)

    Article  Google Scholar 

  36. W. Chan, J. Long, M. Spirito, J. Pekarik, A 60 GHz-band 1v 11.5dbm power amplifier with 11 conference – digest of technical papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 380–381

    Google Scholar 

  37. B. Martineau, V. Knopik, A. Siligaris, F. Gianesello, D. Belot, A 53-to-68 GHz 18dbm power amplifier with an 8-way combiner in standard 65 nm CMOS, in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010. IEEE International, 2010, pp. 428–429

    Google Scholar 

  38. E. Cohen, S. Ravid, D. Ritter, 60 GHz 45nm pa for linear ofdm signal with predistortion correction achieving 6.1. Radio Frequency Integrated Circuits Symposium, 2009. RFIC 2009. IEEE, 2009

    Google Scholar 

  39. K. Raczkowski, S. Thijs, W. De Raedt, B. Nauwelaers, and P. Wambacq, 50-to-67 GHz ESD-protected power amplifiers in digital 45 nm lp CMOS, in Solid-State Circuits Conference – digest of Technical Papers, 2009. ISSCC 2009. IEEE International, 2009, pp. 382–383, 383a

    Google Scholar 

  40. T. Kjellberg, M. Abbasi, M. Ferndahl, A. de Graauw, E. van der Heijden, H. Zirath, A compact cascode power amplifier in 45-nm CMOS for 60 GHz wireless systems, in Compound Semiconductor Integrated Circuit Symposium, 2009. CISC 2009. Annual IEEE, 2009, pp. 1–4

    Google Scholar 

  41. M. Abbasi, T. Kjellberg, A. de Graauw, E. van der Heijden, R. Roovers, H. Zirath, A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60 GHz system-on-chip, in Radio Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, May 2010, pp. 533–536

    Google Scholar 

  42. H.-H. Hsieh, Y.-C. Hsu, L.-H. Lu, A 15/30 GHz dual-band multiphase voltage-controlled oscillator in 0.18-μm CMOS. IEEE Trans. Microw. Theory Tech. 55(3), 474–483 (2007)

    Article  Google Scholar 

  43. Y.-N. Jen, J.-H. Tsai, T.-W. Huang, H. Wang, Design and analysis of a 55-71 GHz compact and broadband distributed active transformer power amplifier in 90-nm CMOS process. Microw. Theory Tech., IEEE Trans. 57(7), 1637–1646 (2009)

    Article  Google Scholar 

Download references

Acknowledgement

The author would like to thank Hammad M. Cheema, Jaap Essing, Pooyan Sakian, Erwin Janssen from Department of Electrical Engineering, Eindhoven University of Technology, The Netherlands; Anton de Graauw and Edwin van der Heijden from NXP Semiconductors, the Netherlands; and Paul T.M. van Zeijl from Philips Research, The Netherlands, for contribution to this work, NXP Semiconductors and Philips research for giving access to the CMOS technologies and STW for the financial support.

Author information

Authors and Affiliations

  1. Department of Electrical Engineering, Eindhoven University of Technology, Den Doleh 2 E. H. 5. 26, 5600 MB, Eindhoven, The Netherlands

    Reza Mahmoudi & Arthur van Roermund

Authors
  1. Reza Mahmoudi
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Arthur van Roermund
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Reza Mahmoudi .

Editor information

Editors and Affiliations

  1. , Dept. Elektrotechniek, K.U.Leuven, Kardinaal Mercierlaan 94, HEVERLEE, B-3001, Belgium

    Michiel Steyaert

  2. Electrical Engineering, Mixed-signal Microelectronics Group, Technical University Eindhoven, Eindhoven, 5600 MB, Netherlands

    Arthur van Roermund

  3. , Department of Physics, University of Milan-Bicocca, Milan, Italy

    Andrea Baschirotto

Rights and permissions

Reprints and permissions

Copyright information

© 2012 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Mahmoudi, R., van Roermund, A. (2012). Ultra High Data Rate CMOS Front Ends. In: Steyaert, M., van Roermund, A., Baschirotto, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1926-2_11

Download citation

  • DOI: https://doi.org/10.1007/978-94-007-1926-2_11

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-94-007-1925-5

  • Online ISBN: 978-94-007-1926-2

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation