Abstract
Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip (SoC) which supports high degree of scalability and reusability. One of the most important issues in an NoC design is how to map an application on NoC-based architecture in order to satisfy the performance and cost requirements. In this paper a novel procedure is introduced to find an optimal application-specific NoC using Particle Swarm Optimization (PSO) and a linear function which considers communication cost, robustness index and contention factor. Communication cost is a common metric in evaluation of different mapping algorithms which have direct impact on power consumption and performance of the mapped NoC. Robustness index is used as a criterion for estimating fault-tolerant properties of NoCs and contention factor highly affects the latency, throughput and communication energy consumption. The experimental results on two real core graphs VOPD and MPEG-4 reveal the power of proposed procedure to explore design space and how effective designer can customize and prioritize the impact of metrics.
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This chapter is an extended version of the paper [10] published at the proceedings of The World Congress on Engineering 2010, WCE 2010, London, UK.
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Fekr, A.R., Janidarmian, M., Bokharaei, V.S., Khademzadeh, A. (2011). Yield Enhancement with a Novel Method in Design of Application-Specific Networks on Chips. In: Ao, SI., Gelman, L. (eds) Electrical Engineering and Applied Computing. Lecture Notes in Electrical Engineering, vol 90. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-1192-1_21
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DOI: https://doi.org/10.1007/978-94-007-1192-1_21
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